Sram design engineer Job at AMD (Boxborough, Massachusetts)

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

5+ years of ASIC and/or physical design flow development experience
Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
Scripting experience with Python, Tcl, or Perl
Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design

Job Responsibility

Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Fulltime

Microprocessor VLSI Physical Design Engineer

At AMD, our mission is to build great products that accelerate next-generation c...

Location

United States , Fort Collins

Salary:

139360.00 - 209040.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

BS/MS in EE, CS, CSE (or similar), plus 8+ years hardware design experience
Hands-on experience in high-speed VLSI design
Excellent understanding of computer architecture, hardware concepts & design tradeoffs required
Knowledge of Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, electromigration, Physical Verification and Sign Off
Comprehend complex Verilog RTL and make minor modifications for timing or power
Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM
Familiar with programing languages such as Perl, C, tcl, etc.

Job Responsibility

Technical lead for high-speed VLSI design in deep sub-micron processes
Work closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule
Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization
Create technical presentations for peers and management
Guide and mentor junior engineers.

Fulltime

New

Memory Design Engineer - SRAM / TCAM

The Memory Circuit Design Engineer is responsible for designing, developing, and...

Location

Taiwan , ZHUBEI

Salary:

Not provided

Cisco

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field
5+ years’ relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles
TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes
Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation
Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys)
Ability to work collaboratively in cross-functional teams
Strong documentation and communication skills in Chinese and English

Job Responsibility

Design and develop memory circuits including SRAM, and other memory technologies
Create detailed circuit schematics, and simulations to validate design functionality
Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration
Conduct prototype development, testing, and debugging to optimize circuit performance and reliability
Maintain comprehensive documentation of design processes, test results, and project schedules
Ensure compliance with industry standards, safety regulations, and company policies
Stay updated with the latest technological advancements and trends in memory circuit design
Participate in design reviews and provide technical guidance to junior engineers
Support troubleshooting and resolution of memory-related issues in hardware products

Principal Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
Over 5+ years of experience in the area of Power analysis and Low power optimization
Over 5+ years of experience in the areas of micro-architecture or Logic and/or SRAM register-file, Clocking

Job Responsibility

Work with the architecture and micro-architecture leads to identify and propose new Power Optimization ideas and trade-offs
Prepare input collaterals including appropriate Logic stimuli for Prime Power RTL and PTPX PD flows
Collaborate with central Flow/methodology team to pilot new power flows
Power-performance analysis
Roll up SoC level Power models
Generate Thermal maps
Project power for future generation of SoC based on architecture changes and appropriate scaling techniques from the past projects across different technology nodes
Define Voltage and frequency targets to fit Power budgets
Influence designs in the areas of Logic memories, interconnects and clocking for optimal SoC power.

Fulltime

New

Senior SoC/ASIC Physical Design Engineer

About the Job: We are seeking a highly skilled Senior SoC/ASIC Physical Design E...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (Master’s preferred)
10+ years of experience in ASIC/SoC physical design and flow development
Expertise in RTL-to-GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools, understanding tool capabilities and underlying algorithms
Proficient in physical design methodologies: synthesis, place & route, STA, formal verification, CDC, and power analysis
Knowledge of FinFET and deep sub-micron CMOS technologies, including power dissipation, leakage, and dynamic behavior
Familiarity with DFT, Scan, MBIST, and LBIST methodologies and their impact on physical design
Proficient in scripting languages (Python, Tcl, Perl, bash/csh) and automation using Makefiles
Skilled in extraction and analysis of design parameters, QOR metrics, and implementing voltage scaling (SVS, DVFS) and SRAM split rail architectures
Proven ability to work collaboratively in dynamic environments, lead design closure activities, and drive execution with a proactive, solution-oriented mindset

Job Responsibility

Develop and Implement PD Flow: Establish a modern physical design (PD) flow utilizing the latest EDA tool fusion and machine learning (ML) techniques to maximize PPA efficiency, optimize resource allocation, and achieve industry-leading time-to-closure and tapeout
End-to-End Physical Design Execution: Perform partition synthesis and physical implementation, including synthesis, floorplanning, power/ground grid generation, place & route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks
Methodology and Automation: Create and refine physical design methodologies and automation scripts to streamline implementation and signoff processes
Cross-Functional Collaboration: Work closely with RTL, DFT, and ASIC design teams to define architectural feasibility, establish timing, power, and area targets, and explore design trade-offs
Drive Design Closure: Utilize an objective, metrics-driven approach to resolve design, timing, and flow issues and ensure predictability in achieving project milestones
Signoff Ownership: Lead signoff closure activities, including static timing analysis (STA), noise analysis, logic equivalency, physical verification, and power integrity (EM/IR)

What we offer

We provide competitive compensation package

ASIC Design Architect

We are seeking a highly experienced ASIC Networking Architect to join our archit...

Location

United States

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. Ph.D. is a plus
Minimum 10+ years in ASIC architecture, with a focus on networking, computing, or high-performance data processing
Strong Background in: Computer Architecture: Multicore processing, memory hierarchy optimizations, hardware-software co-design
Networking Protocols: Ethernet, TCP/IP, BGP, MPLS, VXLAN, QoS, congestion control mechanisms
ASIC Development Lifecycle: RTL design (Verilog/SystemVerilog), verification methodologies (UVM), synthesis, P&R constraints, and tape-out experience
High-Speed Interfaces: PCIe Gen6, SerDes, CXL, HBM integration
Security & Virtualization: Hardware acceleration for secure packet processing, hypervisor optimizations, and virtual network functions
Leadership & Collaboration Skills: Experience working with cross-functional teams spanning hardware, software, and systems
Strong problem-solving and analytical abilities with a track record of delivering complex ASIC projects

Job Responsibility

Architecture Definition: Develop the micro-architecture and high-level design of networking ASICs, ensuring alignment with product goals, performance targets, and industry standards
Networking Protocols & Technologies: Design ASICs that support Ethernet (200G/400G/800G+), Programmability, and AI-driven networking enhancements
Computer Architecture & Memory Subsystems: Optimize packet processing pipelines, caching strategies, memory architectures (HBM, DDR, TCAM, SRAM), and interconnect fabrics for high-bandwidth, low-latency performance
ASIC Design Collaboration: Work with logic design, verification, and physical design teams to ensure smooth RTL implementation, synthesis, timing closure, and signoff
Performance Analysis & Optimization: Use simulation and emulation tools to model ASIC performance, validate system throughput, and optimize power/performance trade-offs
Security & Reliability Features: Implement security mechanisms such as MACSec, IPsec, and deep packet inspection for trusted networking solutions
Industry Trends & Future Technologies: Stay ahead of advancements in disaggregated networking, hardware acceleration (DPUs, SmartNICs), AI-driven networking, and software-defined infrastructure to influence long-term ASIC roadmaps
Technical Leadership: Drive architectural innovation and mentor engineers in design methodologies, ASIC lifecycle best practices, and system integration challenges
Influence Business decisions: Leverages recognized domain expertise, business acumen, and experience to influence decisions of executive business leadership, outsourced development partners, and industry standards groups

What we offer

Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing
Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division
Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good

Fulltime

Senior VLSI Product and Test Engineer

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. ...

Location

United States , Sunnyvale

Salary:

175000.00 - 275000.00 USD / Year

Cerebras Systems

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
10+ years of hands-on experience in semiconductor test engineering with a focus on large-scale integration
Proven track record in wafer-scale testing, AI/ML accelerator testing, or large parallel processor/GPUs with SRAM, DDR-DRAM, HBM
Expert-level Advantest 93K experience with Teradyne as an alternative
Experienced in advanced interconnect testing (mesh networks, NoC, high-speed serial links)
Expertise in High-Speed Serdes testing at ATE, package, and system level
Experience in handling analog blocks in large digital ASICs
Expertise in load-board and probe-card specification, design, development, and debug for advanced DFT implementation that comprises boundary scan, scan, BIST, ATPG, and functional tests
Test program development and optimization
Production test debugging, and yield improvement

Job Responsibility

Design and develop comprehensive test programs for wafer-scale processors and large-scale AI/ML accelerator chips
Implement sophisticated DFT strategies for wafer-scale designs, including hierarchical scan chains and distributed BIST
Create scalable test methodologies for testing hundreds to thousands of processing cores on a single wafer, with distributed SRAM
Develop fault isolation techniques for identifying defective cores/tiles within wafer-scale processors
Implement efficient wafer-level test flows that can handle massive parallelism and complex interconnect structures such as mesh networks, on-chip NoC, and die-to-die communication
Work with the DFT engineers, silicon architects/designers, performance engineers, and software engineers to enhance the testability of Wafer Scale Engines
Work refining test programs for di/dt, V-F characterization space, current and temperature limits
Optimize test programs for testing multiple die simultaneously while maintaining test quality
Develop innovative approaches for power delivery and thermal management during wafer-level testing
Develop test strategies for wafer-scale integration-testing, yield optimization, redundancy, and fault tolerance verification

What we offer

Bonus and equity
Build a breakthrough AI platform beyond the constraints of the GPU
Publish and open source their cutting-edge AI research
Work on one of the fastest AI supercomputers in the world
Enjoy job stability with startup vitality
Simple, non-corporate work culture that respects individual beliefs

Fulltime

New

Primary teaching assistant

Are you looking for a rewarding role in local Primary schools? Do you want the f...

Location

United Kingdom , Plymouth

Salary:

Not provided

Randstad

Expiration Date

April 09, 2026

Requirements

Previous experience working with children (schools, nurseries, sports coaching, or youth groups)
An enhanced DBS on the update service (or the willingness to apply for one)
A good standard of English and Maths to support Primary-aged learners

Job Responsibility

Classroom Support: Assisting the teacher with lesson setup and helping pupils stay on task
Core Skills: Supporting small groups with reading, writing, and phonics (KS1) or numeracy and literacy (KS2)
Early Years/KS1: Helping younger children learn through play and develop their social skills
Well-being: Providing a supportive environment and helping with lunchtime or playground supervision

What we offer

Great Pay: Earn £90 - £95 per day with no hidden fees and weekly pay
Ultimate Flexibility: Manage your own diary-perfect for parents, students, or those seeking a better work-life balance
Zero Admin: No planning, no marking, and no parents' evenings
Variety: Experience different school cultures across Plymouth and find the setting that suits you best
training and education
Safeguarding and Prevent

Sram design engineer

AMD

Location:
United States , Boxborough, Massachusetts

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
March 25, 2026

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Sram design engineer

AMD

Location:United States , Boxborough, Massachusetts

Category:IT - Software Development

Contract Type:Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:March 25, 2026

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March 25, 2026