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Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking an HBM/DDRx Phy expert with role in the definition, design and validation of AWS next generation ML Chips, Cards and server integration. As a senior member of our platform development team, you will have the outstanding and meaningful opportunity to participate in the design and execution of all HBM, Memories and Serdes topics, with the goal of creating and customized platforms that fit within AWS datacenter’s world leading technology. The HBM lead Engineer will need to independently work with vendors, understand the settings, write/modify tests, debug and collect data in the fleet.
Job Responsibility:
As a senior member of the team, you will join a group of hardworking engineers to design and implement innovative next generation machine learning chips and servers. In this position, you will make a real impact in a dynamic, technology focused team. Your work will impact the growing field of machine learning
As a senior member of the team, you will collaborate with architects, design teams, software engineers to deliver the next generation ML chip. In this position, you will have the opportunity to be responsible for IP integration, 2.5D design, bring up, Characterization and validation
A day in the life of an ASIC Engineer on the AWS Organization team focuses on operational excellence, constructively identifying problems and proposing solutions. You help your team evolve by actively participating in the code review process, design discussions, team planning, and ticket/metric/COE reviews. ASIC Engineers will also mentor and help to develop others and interview for the team.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Systems Engineering, or related fields
Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area
Experience working with and managing third party vendors
7+ years of experience in Silicon development
3+ years in SOC/IO/Subsystems
Good understanding of UCIe at the PHY and controller level
Good knowledge of UCIe training, timing parameters and/or controller features
Drive the IP Integration and design of silicon and 2.5D packaging
Drive cross-functional triage effort on complex functional and performance issues
Take the leadership role in post-silicon bring-up of UCIe-Advanced or Standard
Define boot-up initialization, reset flow, training sequence Perform system-level debug and root-cause analysis through bring-up, characterization, validation and production phase
Nice to have:
MS degree in computer science, electrical engineering, or related field
Experience leading and influencing your team or organization, or experience managing teams
Strong Firmware development skills within embedded environments
Knowledge of UCIe phy and controller related protocols Good communication skills and interpersonal skills
What we offer:
health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)