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WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The NPI Test Engineering team plays a critical role across the full product lifecycle, supporting AECG products from early bring-up through mass production. This role focuses on developing robust, scalable, and cost-effective wafer sort test solutions to ensure high product quality and manufacturing success. The Senior Wafer Sort Test Engineer works cross-functionally with Product Engineering, Characterization, and Pattern Verification teams to drive debug, characterization, and margin analysis activities. Lead pre-silicon test planning including test strategy, coverage definition, and test flow development. Drive post-silicon bring-up, debug, and production readiness. Own wafer sort test solution development from concept through high-volume manufacturing.
Job Responsibility
Develop and integrate wafer sort test programs, including validation and production release
Define test flows, test cases, and coverage to meet product requirements
Execute silicon bring-up, debug, and characterization activities
Perform detailed failure analysis to identify root causes of test issues
Analyze test and manufacturing data to improve yield, quality, and test efficiency
Drive optimization of test time and cost through test flow and methodology improvements
Standardize test processes to enhance scalability and operational efficiency
Lead on-site debug and issue resolution with factory partners and internal teams
Communicate status, risks, and results clearly across cross-functional stakeholders
Requirements
Strong fundamentals in digital/analog circuits and test/measurement concepts
Hands-on experience in semiconductor test engineering
Programming or scripting experience (Python, C/C++, or Java)
Experience in data analysis, statistics, and visualization
Proven ability to debug silicon issues and drive root cause analysis
Experience leading technical discussions and cross-functional collaboration
Ability to work effectively in ambiguous and fast-paced environments
5+ years of experience in semiconductor industry
Bachelor's or Master's degree in electrical engineering, Computer Engineering, or related field