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Sr Physical Design Engineer

United States, Austin Employment contract 162000.00 - 243000.00 USD / Year · Job Posted June 10, 2026
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Job Description

This is an on-site, hybrid opportunity. This is not a remote work opportunity. Ericsson Austin has an exciting opportunity for you in a fast-paced, highly collaborative technical environment. We are looking for a highly detailed person who loves problem solving and can tackle complex timing and power challenges in next-gen SoCs, driving solutions that set new industry benchmarks. Ericsson Silicon develops tailor-made, high-performance solutions for present and future RAN needs. Our Application Specific Integrated Circuits (ASICs) power cutting-edge System on a Chip (SoC) - a game-changer in telecommunications. With signal processors (DSPs) and accelerators, our technology enables high-performance, energy-efficient, and lightweight network solutions. The role will work closely with engineering disciplines in Austin and Sweden to make sure that the final ASIC achieves the goals of the program.

Job Responsibility

  • Be an empowered designer tasked with improving PPA of Ericsson ASICs
  • Evaluate feasibility of architectural features through back end implementation
  • Partner with front end design teams to address timing, power and congestion challenges
  • Deliver a synthesized netlist to ASIC BE vendor, and collaborate with vendor to address physical design tradeoffs
  • Work with DFT and architecture teams to develop timing constraints
  • Provide technical leadership and direction for junior members of the team
  • Participate in defining flows, methods and drive continuous improvement

Requirements

  • 10+ years of physical design experience and minimum of a BS EE/CE
  • Expert in one or many of these areas – Methods to improve PPA, RTL checks and Synthesis, STA Constraints, DFT clocking architecture, Physical design of high speed interface IPs
  • Knowledge of System Verilog or VHDL
  • Accomplished at problem resolution and execution per project plan/needs
  • Prior experience in a Senior or Lead Engineer role, including direct responsibility for guiding and mentoring junior team members and setting technical direction
  • Highly team oriented

Nice to have

  • Good scripting skills in Tcl or Python
  • Knowledge of low power implementation methodology through UPF
  • Knowledge of RTL2GDS methodology in 5nm or below technology nodes

What we offer

  • Annual bonus
  • Choice of three medical plan options and a dental plan option
  • 401(k) Plan with automatic 3% company contribution and matching
  • Basic life insurance and basic accidental death and dismemberment coverage
  • Short-term and long-term disability coverage
  • Stock Purchase Plan
  • 15 days of accrued vacation per year
  • Up to 3 personal days per year
  • 11 annual holidays
  • 8 hours of volunteer time
  • 80 hours of sick time annually
  • Up to 16 weeks of paid maternity leave
  • 6 weeks of parental or adoption leave at 100% of pay
  • Financial wellness programs
  • Educational assistance
  • Matching gifts
  • Recognition programs

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