CrawlJobs Logo

Sr. DFT Design Engineer

amazon.de Logo

Amazon Pforzheim GmbH

Location Icon

Location:
United States , Austin

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Employment contract

Salary Icon

Salary:

159200.00 - 215300.00 USD / Year
Save Job
Save Icon
Apply Position

Job Description:

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for a Sr. DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs.

Job Responsibility:

  • Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
  • Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
  • Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals
  • Mentor and develop junior engineers through code reviews, methodology training, and technical guidance
  • Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up

Requirements:

  • Bachelor's degree in computer science, electrical engineering, or related field
  • 5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks experience
  • Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
  • Experience with automation script development

Nice to have:

  • Master's degree or Ph.D. degree in Electrical Engineering or related field
  • Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
  • Experience with modern ASIC/FPGA design and verification tools
  • Experience with SOC bring-up and post-silicon validation
  • MS degree in computer science, electrical engineering, or related field
  • Experience with gate-level testing and multi-clock design practices (CDC)
  • Good breadth of knowledge in chip design from micro-architecture through physical design
  • Good knowledge of design verification (DV) simulation methodologies
  • Strong programming and scripting skills in Perl, Python or Tcl
  • Experience with industry standard DFT/SCAN/ATPG tools
  • Experience with STA constraints development and analysis for DFT modes
  • Practical experience with silicon debug
What we offer:
  • health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
  • 401(k) matching
  • paid time off
  • parental leave
  • sign-on payments
  • restricted stock units (RSUs)

Additional Information:

Job Posted:
May 05, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Icon
Amazon Pforzheim GmbH - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Sr. DFT Design Engineer

Asic Engineer Sr Staff

Hewlett Packard Enterprise is seeking a seasoned Design-for-Test (DFT) Engineer ...
Location
Location
United States , San Jose
Salary
Salary:
148000.00 - 340500.00 USD / Year
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains
  • deep understanding of fault models: stuck-at, transition, path-delay
  • expertise in scan compression, ATPG, and MBIST architecture
  • experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair
  • proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler
  • simulation experience with Synopsys VCS and Cadence NC-Verilog
  • timing analysis using PrimeTime and Cadence Tempus
  • able to define test constraints and review STA reports to ensure timing closure in test modes
  • debugging with waveform tools such as Novas and SimVision
  • familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF
Job Responsibility
Job Responsibility
  • define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond
  • collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features
  • develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models
  • analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations
  • apply test constraints and perform STA analysis to ensure timing closure in test modes
  • support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF)
  • conduct silicon failure analysis and contribute to system-level debug and yield improvement
  • automate DFT flows and analysis using scripting languages such as Perl and Tcl.
What we offer
What we offer
  • health & wellbeing
  • personal & professional development
  • unconditional inclusion
  • competitive compensation, benefits, and career growth opportunities.
  • Fulltime
Read More
Arrow Right

Staff/ Sr Staff RTL Design Engineer

Synopsys software engineers are key enablers in the world of Electronic Design A...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
synopsys.com Logo
Synopsis Engineering
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 3-5 years of relevant experience in ASIC digital design and verification
  • Proficiency in RTL simulation, logic synthesis, and timing verification tools
  • Deep expertise in UVM, SystemVerilog, and protocol verification (e.g., IEEE1500, IEEE1687, AXI, AMBA)
  • Hands-on experience with VIPs and transactors in simulation and emulation environments
  • Strong understanding of DFT architectures, interconnects, and cache coherency protocols
  • Familiarity with debug tools such as Verdi and workflows for performance analysis
  • Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl
  • Experience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking
Job Responsibility
Job Responsibility
  • Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks
  • Performing digital design validation and functional verification at both block and SoC levels
  • Executing logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs
  • Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing
  • Identifying and troubleshooting design timing and DFT functional issues to optimize chip performance
  • Utilizing and scripting in languages such as Tcl to automate design and verification workflows
  • Defining architecture, logic, test bench designs, and embedded software functions for advanced test and analytics
  • Developing and maintaining technical collateral including test suites, protocol documentation, and debug guides
  • Collaborating with R&D and marketing teams to define new features, drive enhancements, and align product roadmaps
  • Delivering product training, managing customer support cases, and ensuring turnaround time (TAT) metrics are met or exceeded
What we offer
What we offer
  • Comprehensive medical and healthcare plans that work for you and your family
  • In addition to company holidays, we have ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Save for your future with our retirement plans that vary by region and country
  • Competitive salaries
  • Fulltime
Read More
Arrow Right

ASIC Digital Design, Sr Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...
Location
Location
Canada , Nepean
Salary
Salary:
Not provided
synopsys.com Logo
Synopsis Engineering
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Master’s degree in Electrical Engineering or related field
  • At least 5 years of relevant industry experience
  • Proficient in Verilog or VHDL for digital design and verification
  • Strong familiarity with code quality metrics and methodologies
  • Experience in high-speed digital and mixed-signal design, including asynchronous clock crossings and DFT methodologies
  • Deep understanding of CDC, synthesis, and power optimization techniques
  • Simulation experience and the ability to debug collaboratively with verification teams
  • Excellent organizational and communication skills, with the ability to interface with various design groups and customer support teams
Job Responsibility
Job Responsibility
  • Designing and verifying complex ASIC digital and mixed-signal systems using Verilog or VHDL
  • Analyzing digital and analog specifications to develop robust system-level designs
  • Collaborating on design flow analysis for CDC, synthesis, DFT, and low power methodologies to optimize performance and reliability
  • Developing, executing, and tracking comprehensive test plans to ensure thorough verification coverage
  • Performing and analyzing functional, assertion, and code coverage to validate design integrity
  • Investigating failure cases, debugging issues, and running gate-level simulations to drive resolution and product quality
  • Working closely with cross-disciplinary teams to ensure seamless integration and alignment across the design lifecycle
What we offer
What we offer
  • Comprehensive medical and healthcare plans
  • ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Retirement plans
  • Competitive salaries
  • Fulltime
Read More
Arrow Right

Sr. Product Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Job Responsibility
Job Responsibility
  • Part of a larger team that correlates test solution to lab/OSAT/customer platform to validate silicon design, process, package, and manufacturability to product specifications
  • Collaborate with cross-functional teams across the supply chain to ensure operational readiness and successful new product introduction (NPI). This include interacting with OSATs and foundries to implement test development and resolve operational and execution issues
  • Develop ATE test methods, characterization, and production test programs
  • Analyse test data to identify test program or silicon issues and working with cross functional teams to root cause will also be a focus
  • Build, and execute silicon characterization on ATE platforms. Perform data analysis and part selection criteria for efficiency and optimization of characterization efforts
  • Production ramp which includes meeting yield, test time, DPPM and managing of product RMA
  • Fulltime
Read More
Arrow Right
New

Sr. Manager ASIC

Annapurna Labs designs silicon and software that accelerates innovation. Custome...
Location
Location
United States , Austin; Cupertino
Salary
Salary:
208300.00 - 281800.00 USD / Year
amazon.de Logo
Amazon Pforzheim GmbH
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Experience delivering cross functional projects
  • 10+ years of equivalent experience
  • 3+ years of people management experience
  • Experience leading and interacting with cross-functional teams
  • Deep technical expertise in SOC integration and methodology
  • Track record of successful tape-outs in leading edge nodes
Job Responsibility
Job Responsibility
  • Lead and grow a team of SOC integration engineers responsible for critical deliverables in our ML accelerator chips
  • Drive technical decisions across multiple disciplines (RTL, timing, DFT, physical design)
  • Ensure on-time delivery of complex SOC integration milestones
  • Establish and maintain best practices for top-level integration, including clock/reset architecture, CDC methodology, and quality metrics
  • Interface with various stakeholders including architecture, verification, and physical design teams
What we offer
What we offer
  • health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
  • 401(k) matching
  • paid time off
  • parental leave
  • sign-on payments
  • restricted stock units (RSUs)
  • Fulltime
Read More
Arrow Right
New

Finance Graduate Program

Are you a Finance enthusiast and keen to get to know Amazon’s Finance organizati...
Location
Location
Germany , Munich
Salary
Salary:
Not provided
amazon.de Logo
Amazon Pforzheim GmbH
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Finance, Business, Economics, Engineering, or Mathematics
  • Final-year student or degree completed within the last 24 months
  • Previous practical experience in Finance (e.g., internships or working student roles)
  • Proficiency in Excel (VLOOKUP, INDEX/MATCH, Pivot Tables, etc.)
  • Fluent English (C1-C2)
  • You must have the right to work in the country of employment.
Job Responsibility
Job Responsibility
  • You will own the financial responsibility for a multi-million-dollar product line in one of our retail categories
  • You will learn about the retail P&L, core KPIs and main Retail Finance IT systems and work with different business teams improving our customer experience
  • The rotation includes insight into FPA and being the finance business partner of Amazon Operations
  • You deliver robust analysis and insights, connecting data to operations to estimate future scenarios, influencing and shaping business decision making
  • You will learn about working capital management (Accounts Receivable & Accounts Payable), business partnering with our vendor managers for specific categories, tools and systems and you will drive and implement large-scale process improvement projects
  • You will gain deep insights in the financial reporting processes including month-end close, statutory reporting and external audits
  • You will get involved in the automation of manual processes and will acquire solid analytical skills of financial statements.
What we offer
What we offer
  • Attractive Total Compensation incl. 28 days of vacation
  • Mobility subsidy: bike share, bike lease, public transport subsidy or "Deutschlandticket" (Germany Transportation ticket)
  • Extra perks with the Amazon Discount Program, such as exclusive Amazon.de discount
  • Gym membership discount
  • Beta testing on new Amazon products
  • free mental health, legal, and financial support for you and your family
  • Get involved: we have with over 13 Amazon Affinity Groups you can join and become an ally to a cause close to your heart (sustainability, diversity, LGBTQ+, mental and/or physical disabilities, local community initiatives, etc.).
  • Fulltime
Read More
Arrow Right
New

University Intern - Housekeeping

Build upon your classroom studies through our Hotel Internship Program opportuni...
Location
Location
Indonesia , Lombok
Salary
Salary:
Not provided
https://www.marriott.com Logo
Marriott Bonvoy
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • You must be a current college or university student.
  • Parttime
Read More
Arrow Right
New

Senior Integration Analyst & Developer

Senior Integration Analyst & Developer (Oracle) Fully Remote 6-month rolling con...
Location
Location
United Kingdom , Greater London
Salary
Salary:
Not provided
outsource-uk.co.uk Logo
Outsource UK
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 6+ years in Oracle Fusion Cloud integrations
  • Strong hands-on OIC development
  • Solid SQL/PLSQL skills
  • Experience with Fusion Finance and Projects modules
  • Familiarity with REST/SOAP APIs and BIP reporting
  • VBCS experience
Job Responsibility
Job Responsibility
  • Delivering end-to-end integrations in OIC
  • Troubleshooting and resolving integration issues
  • Supporting SIT and UAT cycles
  • Working closely with implementation partners to review technical designs and ensure high-quality delivery
  • Fulltime
Read More
Arrow Right