SOC Physical Design Engineer Job at AMD (Shanghai)

Asic Physical Design Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

United States , San Jose

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

BS degree in electrical engineering
computer engineering
or a related field with 7+ years of experience in block or full-chip physical design
Deep design experience in large SoC designs
including IP integration
padring design
bump planning
and RDL routing strategy
Extensive knowledge and practices in Physical Design
including physically aware synthesis

Job Responsibility

Implement physical design at the large SoC chip level from RTL to GDSII
create a design database ready for manufacturing
Interact with IP vendors to understand IP integration requirements and integrate all blocks
IPs
and sub-chips at a large SoC level
Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement
Build full chip floorplan
including pads/ports/bump placement
block placement and optimization
block pins placement and alignment

What we offer

Comprehensive suite of benefits that supports physical
financial and emotional wellbeing
Personal and professional development programs
Unconditional inclusion and flexibility to manage work and personal needs

Fulltime

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical i...

Location

United States , Batavia, Illinois

Salary:

Not provided

NHanced Semiconductors

Expiration Date

Until further notice

Requirements

US Citizenship
5+ years of experience in physical design, specifically in ASIC, SoC, or advanced packaging (2.5D, 3DIC) technologies
Hands-on experience with Git-based version control systems for managing design revisions
Experience with timing closure and signal integrity
Proficiency in Cadence tools for physical design, timing analysis, and signoff
Strong understanding of RTL-to-GDSII flows, including floorplanning, power planning, place-and-route, and timing closure
Working knowledge of parasitic extraction (PEX), power integrity (PI), and thermal analysis in multi-die environments
Ability to work independently with minimal supervision and drive tasks to completion
Excellent verbal and written communication skills for collaboration across engineering teams
Strong debugging skills and ability to analyze tool reports, logs, and simulation results

Job Responsibility

Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
Ensure design compliance with timing, power, and area (PPA) requirements, as well as DFM, DRC, and LVS constraints
Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff
Develop and execute timing closure strategies, working with STA engineers to meet performance goals
Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments
Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration
Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration
Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions
Utilize Git-based version control workflows for design database management and collaborative development
Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

5+ years of ASIC and/or physical design flow development experience
Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
Scripting experience with Python, Tcl, or Perl
Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design

Job Responsibility

Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Fulltime

New

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level
Develop and implement methodologies and strategies to improve physical design efficiency and performance
Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing, physical verification, functional logics equivalence, low power verification and electromigration and IR drop
Implementation of functional ECO with least physical design impact
Design and implement the global clocking scheme at SOC and sub chip levels
Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies
Installation and quality check of internal and external IP collaterals for use by Physical Design execution team
Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers

Fulltime

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

5+ years of ASIC and/or physical design flow development experience
Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
Scripting experience with Python, Tcl, or Perl
Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design

Job Responsibility

Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Fulltime

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Bachelor's or master’s in electrical or computer engineering or related field with 15+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Lead a team in defining implementation and execution plan for a schip/SOC
Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
Drive the to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
Optimizing technology, libraries, physical design, RTL design, and architecture
Leading the team in defining the implementation and execution plan for a subchip/SOC
Collaborating with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects to ensure a cohesive plan
Executing the defined plan to ensure successful tapeout of the subchip/SOC
Driving the team to achieve the best performance, power, and area (PPA) for AI system-on-chips
Optimizing technology choices, libraries, physical design methodologies, RTL design strategies, and architectural decisions to meet performance targets
Ensuring that the physical design aspects align with the overall project goals and timelines

Fulltime

ASIC Engineer, Physical Design

Meta is hiring ASIC Physical Design Engineers within our Infrastructure organiza...

Location

United States , Sunnyvale

Salary:

146000.00 - 209000.00 USD / Year

New

Lead Soc Physical Design Engineer

As a member of the Strategic Silicon Solution Group Full Chip Physical Design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Minimum 15+ years of relevant work experience
Expertise in ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
Should have worked as a go to person or technical lead for at least few full chip projects
Strong technical leadership and ability to mentor/guide/coach design engineers
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
Experience in 5nm & below technologies
Hands-on in reference flows, excellent debugging skills

Job Responsibility

Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing
Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
Full chip / sub system level Clock tree synthesis and advanced clock tree implementation
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence

SOC Physical Design Engineer

AMD

Location:
China , Shanghai

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
March 19, 2026

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