SOC Engineer Job at Robert Half (Columbus)

SOC Design Engineering Manager

This position is for a SoC design Manager - ARM Core and other IP based SOC bloc...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proven leadership experience managing distributed engineering teams
Strong mentoring and coaching skills
Hands-on experience in SoC design from a contemporary product company
16 + years of experience in RTL Design and Integration
Expertise in performance optimization (client, server, system, or embedded)
Solid background in system and software engineering
Excellent communication skills
Strong analytical and problem-solving abilities
Self-motivated and proactive in driving initiatives
Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering

Job Responsibility

Lead a high-performance engineering team designing Processor (ARM, RISC-V) subsystems for AMD/AECG SoCs
Drive end-to-end SoC design and delivery from concept to production
Build and nurture a talented team, fostering growth and technical excellence
Ensure timely delivery of projects while meeting quality standards
Collaborate with cross-functional leaders to achieve organizational goals
Provide strong technical and managerial support to internal and external stakeholders

Firmware Engineer – GPU & SOC Architecture

The focus of this role is to be the technical lead on assigned projects for the ...

Location

Canada , Markham

Salary:

121280.00 - 181920.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Proficient in writing efficient firmware in assembly or C language, including use of a source control system
Proficient in debugging firmware and RTL code using simulation tools, including the ability to determine if the root cause of a failing test is the Firmware, hardware, or test
Experienced in RTL level ASIC design
Experience in Verilog, System Verilog, and working in the Windows and Linux environment
Bachelors or Masters degree (preferred) in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Job Responsibility

Design, develop, debug, verify and/or validate firmware, software and/or hardware
Participant in day-to-day firmware development work
Provide consultation to internal and external customers regarding AMD features and programming requirements

Fulltime

Manager Silicon Design Engineering

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

10 to 15 years of experience in digital ASIC/SOC design verification
4 to 5 years manager experiences on ASIC/SOC design and verification
Experience working with a distributed team
Strong mentoring and coaching skills
Proven experience managing and leading engineering teams
Prior experience in optimizing performance (client, server, system, or embedded)
Strong system and software engineering background
Strong communications skills
Strong analytic and problem-solving skills
Must be a self-starter and self-motivated

Job Responsibility

Lead a high-performance engineering team
Form a team and nurture talents
Lead team, meet schedule commitments and provide strong support to various SoC
Collaborate with multi-functional leaders to drive AMD's success

Staff Engineer, ASIC Development Engineering

Sandisk understands how people and businesses consume data and we relentlessly i...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical/Electronic Engineering or a related field
4-8 years of experience in digital design, with a strong focus on RTL design and integration for complex SoCs
Expert-level proficiency in Verilog/SystemVerilog
Deep understanding of AMBA protocols (AXI/AHB/APB), interconnects, and peripherals
Experience in ASIC verification, Expertise in System Verilog and UVM, Verilog
Experience in IP level verification, testbench architecture development, Testbench component developments
Expertise in coverage closer, code coverage, functional coverage
Experience in Gate level simulations
Knowledge on serial protocols UFS, PCIe, USB, MIPI or any other serial protocol
Knowledge on memory protocols - SD, eMMC, Flash etc

Job Responsibility

Define verification plan, create testbenches, testcases, gate level simulations etc independently

Fulltime

Asic Physical Design Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

United States , San Jose

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

BS degree in electrical engineering
computer engineering
or a related field with 7+ years of experience in block or full-chip physical design
Deep design experience in large SoC designs
including IP integration
padring design
bump planning
and RDL routing strategy
Extensive knowledge and practices in Physical Design
including physically aware synthesis

Job Responsibility

Implement physical design at the large SoC chip level from RTL to GDSII
create a design database ready for manufacturing
Interact with IP vendors to understand IP integration requirements and integrate all blocks
IPs
and sub-chips at a large SoC level
Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement
Build full chip floorplan
including pads/ports/bump placement
block placement and optimization
block pins placement and alignment

What we offer

Comprehensive suite of benefits that supports physical
financial and emotional wellbeing
Personal and professional development programs
Unconditional inclusion and flexibility to manage work and personal needs

Fulltime

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Security Engineer

Airspace Link is seeking a Security Engineer to support the security posture of ...

Location

United States , Detroit

Salary:

Not provided

Airspace Link

Expiration Date

Until further notice

Requirements

2–5 years of experience in security engineering, cloud security, SOC/IR operations, or related hands-on security roles
Working knowledge of Azure security concepts and Microsoft cloud security tools
Practical experience with: Microsoft Defender for Cloud, Endpoint, Identity, and Cloud Apps
Microsoft Sentinel (KQL querying, incident investigation, dashboards)
Microsoft Intune / Endpoint Manager (MDM/MAM)
Microsoft Purview (DLP and compliance tooling)
Hands-on experience supporting vulnerability remediation with engineering teams
Familiarity with Terraform, secure CI/CD practices, and cloud configuration management
Strong written and verbal communication skills with the ability to collaborate cross-functionally

Job Responsibility

Assist with implementing and maintaining security controls within Azure and SaaS environments
Support the incident response lifecycle, including initial investigation, coordination with engineering, and documentation of remediation actions
Monitor, tune, and assist in the operation of the Microsoft Defender suite (Defender for Cloud, Endpoint, Identity, Cloud Apps, and Vulnerability Management)
Support mobile device management (MDM) and endpoint compliance using Microsoft Intune and Endpoint Manager
Partner with engineering teams to identify, prioritize, and track remediation of vulnerabilities across applications, cloud infrastructure, and CI/CD pipelines
Help implement and maintain Entra ID Conditional Access and Privileged Identity Management (PIM)
Assist in integrating DevSecOps guardrails within Azure DevOps and GitHub pipelines (e.g., CodeQL, IaC scanning, secret governance)
Participate in developing dashboards and analytics in Microsoft Sentinel, including KQL queries and incident correlation support
Contribute to threat modeling and risk assessments as part of project reviews
Support the creation and upkeep of security configuration baselines, Terraform modules, and policy templates

Fulltime

Technologist, ASIC Development Engineering

We are looking for a highly skilled and experienced individual for SoC PD lead p...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs
Proven ability in technically leading a small/medium-sized team for executing projects preferred
Hands-on experience on the entire PD Flow from RTL to GDSII
Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains
Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
Exposure to static timing analysis fixes including automated ECO generation
Strong in areas on CTS, Power, Bump planning, Floorplan
Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies
Library preparation in any environment (Synopsys, Cadence, etc)

Job Responsibility

To be responsible for leading RTL-to-GDSII SoC implementation effort
To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.
To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity
To ensure process compliance during project execution and enable / participate in technical discussions/reviews
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow
Foster a culture of innovation, collaboration, and continuous improvement

Fulltime

SOC Engineer

Robert Half

Location:
United States , Columbus

Category:
IT - Administration

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
March 12, 2026

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