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As a member of the AECG-Embedded X86 SOC architecture team, you will help bring to life cutting-edge designs. You will work closely with IP design, Physical Design teams, and product engineers to achieve first pass silicon success.
Job Responsibility
Lead SoC architecture: define processor complex, interconnect/NoC, memory controllers/DRAM topology, IOMMU hierarchy, security islands, and subsystem boundaries
write clear architecture specifications and drive reviews to closure
Own platform power & reset intent: specify PWROK/PWROKRAW/reset/iso sequencing across rails and domains
ensure asynchronous PWROK de‑assertion behavior meets EGADS and safety requirements
partner with board/VR teams and FCH/ART owners
SOC Features ownership: Define and drive SOC features
Static timing analysis definitions: work with IP, process and product teams to define STA strategies
High‑speed I/O architecture: architect PCIe Gen5/Gen6 RC/EP topologies, NTB links, Ethernet MAC/PHY integration, clocking, lane bifurcation, and PHY interfaces
align controller programming models with NBIO/SYSHUB wrappers
Performance, power, and reliability modeling: establish CAC targets for GFX/NPU, guard‑bands/aging models using ARO/RO monitors, and close V/F/tj operating points with mission profiles
collaborate with quality teams on long‑life reliability
Functional safety (FuSa) & RAS: work with IP teams to allocate FuSa and RAS requirements, trace to Jama/PRS, and align external auditors and customer expectations
ensure ISO‑26262 compliance plans are executable
Cross‑functional leadership: partner with program management and customer engineers on headline specs (CPU/GPU/NoC sizing, DRAM speed/width, PCIe/Ethernet/NTB), schedules, and deliverables
clarify AMD vs. customer roles and responsibilities