Silicon Validation Engineer Job at Meta (Sunnyvale)

Silicon Design Engineer

This position requires a deep understanding of device physics, components design...

Location

Taiwan , Hsinchu

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors degree in engineering or physical science, preferably with advanced degree (MS or PhD)
Working experience in baseband and RF component design and modeling
Proficiency in industry-standard EDA tools including Cadence Virtuoso, Spectre, and HSPICE
Strong background in SPICE modeling and QA for semiconductor devices
Familiar with foundry PDKs, parasitic extraction, and physical verification flows
Experience with EM simulation and modeling tools such as HFSS, EMX and ICCAP
Working knowledge of FinFET and GAA technologies at 3nm, 2nm, and beyond

Job Responsibility

Perform device characterization, SPICE modeling and simulation support to FPGA product design
Responsible for design, optimize, and validate baseband and RF components in advanced CMOS nodes
Perform schematic design and simulations using Cadence Virtuoso, Spectre, and HSPICE
Guide and review layout implementation to ensure optimal device performance and manufacturability
Analyze silicon measurement data and correlate with simulation models to enhance design accuracy
Conduct SPICE and EM modeling using tools such as ICCAP, HFSS or EMX
Explore and evaluate stacked-die and 3DIC technologies, including simulation, modeling and layout consideration for heterogeneous integration
Collaborate with foundry and internal teams to utilize and validate PDKs, perform parasitic extraction, and ensure physical verification compliance

Lead Test Development Engineer

Lead the definition and implementation of manufacturing test solutions, developi...

Location

United States , Santa Clara

Salary:

Not provided

Achronix Semiconductor

Expiration Date

Until further notice

Requirements

10+ years of experience in DFT, testing, or silicon validation
Solid understanding of scan insertion, ATPG, MBIST, and fault models
Experience with Synopsys TestMax, Siemens Tessent, and similar DFT EDA tools
Proficiency with JTAG, boundary scan, and related IEEE standards (1149.1, 1149.6)
Hands-on experience with ATPG, MBIST and functional pattern generation, simulation, and verification
Familiarity with script-based test case generators and industry-standard test pattern formats (WGL, STIL)
Proficiency in scripting languages (Python, Perl, or Tcl)
Strong debugging and problem-solving skills for silicon and test issues

Job Responsibility

Define and implement DFT architecture (scan, boundary scan, MBIST)
Collaborate with design and physical design teams to ensure integration and verification of DFT features
Design and implement test mode controls and access mechanisms
Generate and validate ATPG patterns for various fault types
Generate test cases targeting specific FPGA blocks and IP
Work with IP vendors to integrate testing solutions for external memory interfaces and high-speed I/O
Perform fault coverage analysis and implement improvements
Conduct gate-level simulations with test patterns
Perform silicon test pattern bring-up, validation, and debugging on lab bench and ATE platforms
Implement and debug scan, BIST, and functional tests on production testers

Fulltime

New

ASIC Engineer, Infra Silicon Pre/Post Silicon Validation

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

Senior SoC HW (Functional) Validation Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Applied understanding of Computer Architecture and CPU/SoC validation principles, including: Understanding of SoC subsystem, SoC system level, and platform level functionality and writing scripts/software with industry standard languages like Python or C/C++
At least 5+ years of experience
Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams
Verification, logic development, validation, or validation tools experience as part of a CPU, SoC and/or IP development team
Leadership skills
Demonstrated validation expertise in one or more of the following: Functional: Core, cache Coherency/mesh/fabric, PCIe/ IO, Memory Controller, Power Management
Power and Performance
Automation, Content Creation, or Tools/Scripts Development

Job Responsibility

Own post-silicon validation of one of the following areas – functional validation of cache Coherency/mesh/fabric
Define, guide, and contribute to the implementation of silicon debug tools and capabilities
Become an expert on the overall architecture, implementation of complex features/flows/protocols, and their interactions with other parts of the SoC, with the platform, and with software
Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise
Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements
Apply your knowledge of validation principles and techniques and your judgement to write test plans and implement them by developing test content, scripts, tools and other validation collateral
Execute content in post-silicon, triage and debug failures
Apply your growth mindset to learn and adapt in a complex and dynamic environment
Engage with partners to drive continuous improvement to the design, to validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably
Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers

Fulltime

ASIC Engineer - Infra Silicon Enablement

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

India , Bangalore

Salary:

Not provided