Silicon Validation Engineer Job at Meta (Taipei)

Silicon Design Engineer

This position requires a deep understanding of device physics, components design...

Location

Taiwan , Hsinchu

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors degree in engineering or physical science, preferably with advanced degree (MS or PhD)
Working experience in baseband and RF component design and modeling
Proficiency in industry-standard EDA tools including Cadence Virtuoso, Spectre, and HSPICE
Strong background in SPICE modeling and QA for semiconductor devices
Familiar with foundry PDKs, parasitic extraction, and physical verification flows
Experience with EM simulation and modeling tools such as HFSS, EMX and ICCAP
Working knowledge of FinFET and GAA technologies at 3nm, 2nm, and beyond

Job Responsibility

Perform device characterization, SPICE modeling and simulation support to FPGA product design
Responsible for design, optimize, and validate baseband and RF components in advanced CMOS nodes
Perform schematic design and simulations using Cadence Virtuoso, Spectre, and HSPICE
Guide and review layout implementation to ensure optimal device performance and manufacturability
Analyze silicon measurement data and correlate with simulation models to enhance design accuracy
Conduct SPICE and EM modeling using tools such as ICCAP, HFSS or EMX
Explore and evaluate stacked-die and 3DIC technologies, including simulation, modeling and layout consideration for heterogeneous integration
Collaborate with foundry and internal teams to utilize and validate PDKs, perform parasitic extraction, and ensure physical verification compliance

Lead Test Development Engineer

Lead the definition and implementation of manufacturing test solutions, developi...

Location

United States , Santa Clara

Salary:

Not provided

Achronix Semiconductor

Expiration Date

Until further notice

Requirements

10+ years of experience in DFT, testing, or silicon validation
Solid understanding of scan insertion, ATPG, MBIST, and fault models
Experience with Synopsys TestMax, Siemens Tessent, and similar DFT EDA tools
Proficiency with JTAG, boundary scan, and related IEEE standards (1149.1, 1149.6)
Hands-on experience with ATPG, MBIST and functional pattern generation, simulation, and verification
Familiarity with script-based test case generators and industry-standard test pattern formats (WGL, STIL)
Proficiency in scripting languages (Python, Perl, or Tcl)
Strong debugging and problem-solving skills for silicon and test issues

Job Responsibility

Define and implement DFT architecture (scan, boundary scan, MBIST)
Collaborate with design and physical design teams to ensure integration and verification of DFT features
Design and implement test mode controls and access mechanisms
Generate and validate ATPG patterns for various fault types
Generate test cases targeting specific FPGA blocks and IP
Work with IP vendors to integrate testing solutions for external memory interfaces and high-speed I/O
Perform fault coverage analysis and implement improvements
Conduct gate-level simulations with test patterns
Perform silicon test pattern bring-up, validation, and debugging on lab bench and ATE platforms
Implement and debug scan, BIST, and functional tests on production testers

Fulltime

New

Senior SoC HW (Functional) Validation Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Applied understanding of Computer Architecture and CPU/SoC validation principles, including: Understanding of SoC subsystem, SoC system level, and platform level functionality and writing scripts/software with industry standard languages like Python or C/C++
At least 5+ years of experience
Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams
Verification, logic development, validation, or validation tools experience as part of a CPU, SoC and/or IP development team
Leadership skills
Demonstrated validation expertise in one or more of the following: Functional: Core, cache Coherency/mesh/fabric, PCIe/ IO, Memory Controller, Power Management
Power and Performance
Automation, Content Creation, or Tools/Scripts Development

Job Responsibility

Own post-silicon validation of one of the following areas – functional validation of cache Coherency/mesh/fabric
Define, guide, and contribute to the implementation of silicon debug tools and capabilities
Become an expert on the overall architecture, implementation of complex features/flows/protocols, and their interactions with other parts of the SoC, with the platform, and with software
Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise
Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements
Apply your knowledge of validation principles and techniques and your judgement to write test plans and implement them by developing test content, scripts, tools and other validation collateral
Execute content in post-silicon, triage and debug failures
Apply your growth mindset to learn and adapt in a complex and dynamic environment
Engage with partners to drive continuous improvement to the design, to validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably
Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers

Fulltime

Senior Photonics Design Engineer

As a Photonic Design Engineer at Salience Labs, you will play a crucial role in ...

Location

United Kingdom , Oxford

Salary:

Not provided

Salience Labs

Expiration Date

Until further notice

Requirements

Master’s degree in physics, photonics, electrical engineering, or optical engineering, with 5+ years of relevant experience (Ph.D. preferred)
Strong understanding of waveguide optics, integrated photonic devices, and semiconductor physics
Knowledge of silicon photonic components, with an understanding of their trade-offs
Experience in modelling and simulating integrated photonic devices, using both commercial software and analytical approaches
Excellent communication skills, critical thinking, and self-motivation

Job Responsibility

Designing and modelling passive and active silicon photonic devices and integrated photonic systems, including III-V's
Prototyping novel photonic components and architectures, designing suitable test structures, and validating experimental results against simulations
Using simulation and experimental data to evaluate device performance and guide engineering decisions
Working with the architecture team to develop system-level models for photonic integration
Supporting hardware and software teams to ensure alignment with system-level performance goals
Collaborating with component test engineers to design experiments and analyse results
Helping create and maintain the codebase for photonics component layout in GDS format
Partnering with manufacturing teams to optimise and transition designs into volume production
Contributing to intellectual property development, including filing patents for novel innovations

SOC Validation Engineer

We are looking for a dynamic, energetic SOC Validation Engineer to join our grow...

Location

United States , San Jose

Salary:

157600.00 - 236400.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Hands on experience in pre-silicon validation using FPGA-based prototyping and emulation platforms
Hands on experience in post silicon validation using characterization boards, customer boards
Programming/scripting skills (e.g., C, Perl, Python)
Knowledge of system architecture, technical debug, and validation strategies for ARM and X86 architectures
Experience with silicon and board bring up activities
Experience with board/platform-level debug, protocol level debug
Experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc
Understanding of operating systems (Linux preferred)
Experience with version control systems (Git)
Experience in hardware validation or embedded systems

Job Responsibility

Driving technical innovation to improve AMD’s capabilities across SoC validation
Own the creation of comprehensive test plans and detailed test cases
Manage and execute the overall test plan
Systematically collect, analyze, and report failure data
Collaborate closely with the CFT teams to identify root causes
Ensure the test plan features are covered in both pre-silicon and post-silicon
Support post-silicon bring-up activities and system-level testing
Provide technical assistance in debugging critical issues
Working with multiple teams, and tracking test execution
Working closely with supporting technical teams

Fulltime

Asic Engineer Sr Staff

Hewlett Packard Enterprise is seeking a seasoned Design-for-Test (DFT) Engineer ...

Location

United States , San Jose

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains
deep understanding of fault models: stuck-at, transition, path-delay
expertise in scan compression, ATPG, and MBIST architecture
experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair
proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler
simulation experience with Synopsys VCS and Cadence NC-Verilog
timing analysis using PrimeTime and Cadence Tempus
able to define test constraints and review STA reports to ensure timing closure in test modes
debugging with waveform tools such as Novas and SimVision
familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF

Job Responsibility

define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond
collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features
develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models
analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations
apply test constraints and perform STA analysis to ensure timing closure in test modes
support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF)
conduct silicon failure analysis and contribute to system-level debug and yield improvement
automate DFT flows and analysis using scripting languages such as Perl and Tcl.

What we offer

health & wellbeing
personal & professional development
unconditional inclusion
competitive compensation, benefits, and career growth opportunities.

Fulltime

Validation Execution Engineer

The Validation Execution Engineer is responsible for planning, executing, and re...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience in validation, test engineering, or related lab/automation work (internships count)
Basic understanding of computer architecture and SoC/platform components (CPU/GPU, memory, I/O)
Comfortable in Linux and Windows environments
Experience with lab equipment and tools: oscilloscopes, protocol analyzers (PCIe/USB), or willingness to learn quickly
Strong attention to detail, disciplined test execution, and clear documentation
Python scripting for automation is a plus
Bachelor’s Degree (BS) in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Master’s Degree (MS) preferred

Job Responsibility

Learn AMD silicon and system features
understand new features in silicon, BIOS, firmware, SW, etc. Develop personal technical capability on each IP/Domain
Prepare and configure test environments, including hardware, firmware, drivers, and OS environments (Linux/Windows) according to validation plan’s requirements
Execute functional, stress, performance and regression tests per plan
Perform first-level issue triage, reproduce issues, capture high-quality logs/traces, and document defects clearly
Collaborate with global validation team, developer team and debug team for issue debug, fix verification
Write and maintain Python scripts to automate test execution
Provide concise daily/weekly status updates with coverage progress, defects and risks

New

Mixed-Signal Silicon Program & Supply Manager

We’re hiring a Mixed-Signal Silicon Program & Supply Manager to lead the product...

Location

United Kingdom , Farnborough

Salary:

60000.00 - 70000.00 GBP / Year

BLUESTREAM PEOPLE

Expiration Date

Until further notice

Requirements

Degree in Electrical Engineering, Physics, or similar (MBA a plus)
5+ years in IC manufacturing, supply chain, or post-silicon program management
Experience with mixed-signal ICs, DFT, and silicon validation
Strong coordination skills across teams and suppliers
Proficiency in project tracking tools and clear communication

Job Responsibility

Manage wafer fabrication, packaging, and assembly partners
Oversee logistics and mitigate supply chain risks
Lead post-silicon test and qualification activities
Collaborate with design and test teams to align on productization
Track progress using tools like Jira or MS Project
Ensure quality standards and reliability testing are met

What we offer

Negotiable for the right experience

Fulltime

Silicon Validation Engineer

Meta

Location:
Taiwan , Taipei

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
January 23, 2026

Looking for more opportunities? Search for other job offers that match your skills and interests.

Similar Jobs for Silicon Validation Engineer

Silicon Design Engineer

Lead Test Development Engineer

Senior SoC HW (Functional) Validation Engineer

Senior Photonics Design Engineer

SOC Validation Engineer

Asic Engineer Sr Staff

Validation Execution Engineer

Mixed-Signal Silicon Program & Supply Manager

Silicon Validation Engineer

Meta

Location:Taiwan , Taipei

Category:IT - Software Development

Contract Type:Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:January 23, 2026

Looking for more opportunities? Search for other job offers that match your skills and interests.

Similar Jobs for Silicon Validation Engineer

Silicon Design Engineer

Lead Test Development Engineer

Senior SoC HW (Functional) Validation Engineer

Senior Photonics Design Engineer

SOC Validation Engineer

Asic Engineer Sr Staff

Validation Execution Engineer

Mixed-Signal Silicon Program & Supply Manager

Location:
Taiwan , Taipei

Category:
IT - Software Development

Contract Type:
Not provided

Job Posted:
January 23, 2026