Silicon Design Verification Engineer Job at AMD (San Jose)

Senior Staff Silicon Design Engineer (Design Verification)

At AMD, our mission is to build great products that accelerate next-generation c...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in ASIC/SoC design
Strong hands-on verilog development experience, familiar with scripting languages like Perl
Good experience on complicate hub,control IP design
Strong problem solving, independent thinking, teamwork and communication skills
Bachelor or Master degree in E&E or Computer Engineering. (Preferred Master Degree)

Job Responsibility

Own part of IP feature design with cooperation with other designers
As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.

What we offer

AMD benefits at a glance.

New

Principal Silicon Design Verification Engineer

As a Principal Engineer - ASIC verification in the Data Processing Unit team you...

Location

United States , Santa Clara

Salary:

142800.00 - 304200.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Job Responsibility

As a Principal Engineer in the Data Processing Unit team, you will be validating silicon to solve complex problems in a datacenter
Lead key components of functional validation of complex ASIC SOC using UVM/C test bench
Perform pre-silicon SoC verification, post-silicon validation by defining testing strategies
Work with cross functional teams, architecture, design, verification, partner teams for project execution and influence next generation designs
Develop test plan, C tests and infrastructure to complete functional validation of complex design and report bug/issues
Running tests, debugging failures, creating stress and performance scenarios to meet test plan goals
Actively participate in chip bring up and write test firmware to support various teams
Innovate to improve validation efficiency through methodologies and tools
Coach and mentor others in your areas of expertise
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Fulltime

Senior Silicon Design Verification Engineer

Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verif...

Location

United States , San Jose

Salary:

136000.00 - 204000.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Proven track record in technical leadership of teams with 5+ engineers
Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS requirements
Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium
Require strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management
BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science

Job Responsibility

Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance
Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level
Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs
Develop and execute comprehensive verification plans, including testbenches and test cases
Collaborate with design, architecture, and software teams to define and implement verification strategies
Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification
Mentor and guide junior engineers, fostering a collaborative and innovative team environment

Fulltime

Design Verification Engineer - Azure DPU Silicon

Help build the silicon that powers the Microsoft Cloud. The Azure DPU Silicon te...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

5+ years of experience in ASIC/SoC design verification
Strong proficiency in System Verilog and UVM methodology
Solid understanding of computer architecture, networking, or memory subsystems
Experience with high-speed I/O (PCIe, Ethernet) or NIC/acceleration pipelines preferred
Ability to work in a collaborative, cross-functional environment with strong technical ownership

Job Responsibility

Define and execute block and subsystem-level verification strategy for DPU IPs
Develop SystemVerilog UVM testbenches, environments, and reusable components
Create constrained-random and directed tests, assertions, and functional coverage
Collaborate closely with architecture, RTL design, and post-silicon validation teams
Drive improvements in verification methodology, automation, and debug efficiency
Contribute to system-level validation and co-simulation with software and firmware teams

Fulltime

Staff Silicon Design Engineer (Physical Design)

We are looking for an adaptive, self-motivative Back End Physical Design enginee...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

9 years professional experience in the semiconductor industry
Experience in FinFET & Dual Patterning nodes such as 16/14/12 and sub-10nm nodes
High-frequency design experience
Excellent physical design and timing background
Synopsys Tools Experience Not a Must But Preferred
MNC experience is a plus
Familiarity with all Design areas and tools and solid understanding of design/technology interactions
Good understanding of computer organization/architecture
Strong analytical/problem solving skills and pronounced attention to details
Must be a self-starter, and able to independently drive tasks to completion

Job Responsibility

Involves in Floorplan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
Experience in handling different PNR tools - Synopsys Design Compiler, ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
Involvement in not only Physical design, but also STA & timing closure, authoring methodology scripts in Tcl, Perl and/or Python
Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
Hands on experience on 16nm, 14nm, 12nm, and sub-10nm projects

Fulltime

Silicon Design Engineer

A Front-End Silicon Design and Integration (FEINT) Engineering role in our GFX M...

Location

China , Shanghai

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proven understanding of RTL design, synthesis, and ECO principles
Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, PtPx, etc.
Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile)
Excellent skills with Unix/Linux environment
Familiar with RTL coding techniques for competitive PPA-measured QoR
Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.)
Good understanding of gate level circuit design and physical level design concept and methodology
Familiar with VCS/Verdi
Excellent communication skills in English (both written and oral)
Self motivated, and committed to achievement

Job Responsibility

Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result)
Develop power redux strategy such as hierarchical CG (clock gating) at multiple levels including RTL and gate level, to ensure power target attainment
Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies
Develop, adopt and automate RTL static design rule checks in collaboration with Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team
Develop and adopt FEINT design and verification infrastructure, methodology and tools

What we offer

AMD benefits at a glance

Fulltime

New

Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great prod...

Location

Canada , Vancouver

Salary:

105600.00 - 158400.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Masters or bachelor in electrical or computer engineering

Job Responsibility

Writing/Implementing/Reviewing Test Plans
Developing Testbenches and Verification Components such as UVCs
models
BFMs
and Re-usable Verification Environments
Writing
Modifying
and Maintaining Random and Directed Test Cases and Libraries in System Verilog/UVM
Analyzing Functional and Code Coverage
Implementing Assertions

Fulltime

New

Sr ASIC Design Verification Engineer (NetSec)

As a Design Verification engineer on the ASIC team, you will ensure that the ASI...

Location

United States , Santa Clara

Salary:

Not provided

Palo Alto Networks

Expiration Date

Until further notice

Requirements

BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred
Minimum 5 years experience in ASIC design verification
Demonstrated success in taking multiple ASIC products from concept to mass production
Expertise in SystemVerilog and UVM Technical strength in the following areas is required
Defining test plans, including comprehensive adversarial testing
Developing rich functional coverage models
Creating powerful and scalable test benches Implementing sophisticated self-checking infrastructure with reference models and scoreboards
Developing reusable constrained-random tests
Debugging failures
Closing coverage

Job Responsibility

Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification
Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies
Develop flows, methodologies, and infrastructure for emulation
Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers
Define new tools and methodologies to continuously improve quality and velocity
Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification

What we offer

restricted stock units and a bonus
A description of our employee benefits may be found here

Fulltime

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Silicon Design Verification Engineer

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