Silicon Design Verification Engineer Job at AMD (San Jose)

Silicon Design Engineer

CIT (Chiplet Interconnect Technology) tam delivers industry leading high-perform...

Location

China , Shanghai

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor or MS in EE, ME, CS or related
10+ years of DV experience
Expertise in UVM
Highly motivated, innovative individual with a keen interest in finding and resolving issues
Good written and oral English skills
Good communication skills
Formal verification experience is a plus

Job Responsibility

Create test plans and host the review with all stakeholders
Work on CIT IP module and subsystem level verification
Perform regression/sanity maintain and debug
Support IP deployment in SOC
Support IP bring up on silicon

Manager Silicon Design Engineering

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

10 to 15 years of experience in digital ASIC/SOC design verification
4 to 5 years manager experiences on ASIC/SOC design and verification
Experience working with a distributed team
Strong mentoring and coaching skills
Proven experience managing and leading engineering teams
Prior experience in optimizing performance (client, server, system, or embedded)
Strong system and software engineering background
Strong communications skills
Strong analytic and problem-solving skills
Must be a self-starter and self-motivated

Job Responsibility

Lead a high-performance engineering team
Form a team and nurture talents
Lead team, meet schedule commitments and provide strong support to various SoC
Collaborate with multi-functional leaders to drive AMD's success

Silicon Design Engineer

This position requires a deep understanding of device physics, components design...

Location

Taiwan , Hsinchu

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors degree in engineering or physical science, preferably with advanced degree (MS or PhD)
Working experience in baseband and RF component design and modeling
Proficiency in industry-standard EDA tools including Cadence Virtuoso, Spectre, and HSPICE
Strong background in SPICE modeling and QA for semiconductor devices
Familiar with foundry PDKs, parasitic extraction, and physical verification flows
Experience with EM simulation and modeling tools such as HFSS, EMX and ICCAP
Working knowledge of FinFET and GAA technologies at 3nm, 2nm, and beyond

Job Responsibility

Perform device characterization, SPICE modeling and simulation support to FPGA product design
Responsible for design, optimize, and validate baseband and RF components in advanced CMOS nodes
Perform schematic design and simulations using Cadence Virtuoso, Spectre, and HSPICE
Guide and review layout implementation to ensure optimal device performance and manufacturability
Analyze silicon measurement data and correlate with simulation models to enhance design accuracy
Conduct SPICE and EM modeling using tools such as ICCAP, HFSS or EMX
Explore and evaluate stacked-die and 3DIC technologies, including simulation, modeling and layout consideration for heterogeneous integration
Collaborate with foundry and internal teams to utilize and validate PDKs, perform parasitic extraction, and ensure physical verification compliance

Principal Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
9+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems
5+ years’ industry experience of chip and/or computer architecture
5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl
CPU or Graphics core verification experience
In depth knowledge of verification principles, testbenches, stimulus generation, System Verilog, UVM, and coverage closure

Job Responsibility

Creation of complex verification environments and tests, pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation
Interact with architects and design engineers to create verification plans covering strategy, test environments & tests, and verification requirements for IP/SS/SOC level verification
Create and drive test-plans and test development to provide complete features coverage
Develop and implement technical solutions to complex quality and design challenges
Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage
Triage and debug testbench, simulation, and emulation fails
Develop Makefiles and scripts for scalable and efficient verification
Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment
Collaborate with teams across sites and geographies

Fulltime

Senior Design Verification Engineer

We are looking for a Senior Design Verification Engineer to join Microsoft's Sil...

Location

United States , Raleigh

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check

Job Responsibility

Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components
Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness
Develop Verification IP (VIP) components to verify home grown designs
Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments
Define and implement functional coverage and drive coverage closure
Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third-party vendor teams to ensure pre-and-post-Si testing is comprehensive
Develop scripts for verification and validation infrastructure

Fulltime

New

Senior SOC Debug Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

8+ years of pre-silicon SOC or subsystem or IP verification experience
Candidate must have at least a bachelor’s or master’s degree in electrical, Electronics, Computer Engineering, Computer Science or a related degree
6+ years of verification experience working on CPU/SOC designs, with 2+ years of design for debug verification experience
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Own verification of Design for Debug (DFD) SoC level flows including Task planning and schedule estimation, proactively identifying and removing roadblocks and finding ways to make the team more efficient
Develop verification strategy, requirements, environments, tools, and methodologies
Become an expert on the overall debug architecture, understand customer use models, and understand interactions with other parts of the SOC, with the platform, and with software
Apply your knowledge of verification principles and techniques and your judgement to write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
Run tests, debug failures to root cause, and recommend fixes
Apply your growth mindset to learn and adapt in a complex and dynamic environment
Engage with partners to drive continuous improvement to both the design, to verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably
Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise
Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, post-silicon validators, other verification engineers, and IP and tool providers
Delight your customers by providing high quality results on schedule

Fulltime

Senior Manager Silicon Design Engineer

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

12-15 years full-time experience in IP hardware design
Proven experience managing and leading engineering teams
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
Clock domain crossing (CDC) tools
Detailed understanding of SoC design flows
Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
Outstanding interaction skills while communicating both written and verbally
Ability to work with multi-level functional teams across various geographies
Outstanding problem-solving and analytical skills

Job Responsibility

Lead a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies
Help bring to life cutting-edge designs, working closely with architecture, physical design, and product engineers to achieve first pass silicon success
Design of IP and subsystems with integration of AMD and other 3rd party IPs
Work collaboratively with other members of the IP team to support design verification, implementation, synthesis, constraints, static timing analysis, and delivery to SOC
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up

Principal Verification Engineer

Microsoft is a highly innovative company that collaborates across disciplines to...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

12+ more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in UVM or C++
Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
Scripting language such as Python or Perl

Job Responsibility

Own or lead verification of complex flows at the SOC, subsystem, or IP levels
Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios
Learn about the design and interact with partner teams to define verification strategies and test plans
Develop verification environments and run and debug simulations to drive quality
Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
innovate to improve verification efficiency through methodologies or tools
Coach and mentor others in your areas of expertise
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Fulltime

Silicon Design Verification Engineer

AMD

Location:
United States , San Jose

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
March 20, 2026

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