Silicon Design Engineer Job at AMD (Shanghai)

Silicon Design Engineer

CIT (Chiplet Interconnect Technology) tam delivers industry leading high-perform...

Location

China , Shanghai

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor or MS in EE, ME, CS or related
10+ years of DV experience
Expertise in UVM
Highly motivated, innovative individual with a keen interest in finding and resolving issues
Good written and oral English skills
Good communication skills
Formal verification experience is a plus

Job Responsibility

Create test plans and host the review with all stakeholders
Work on CIT IP module and subsystem level verification
Perform regression/sanity maintain and debug
Support IP deployment in SOC
Support IP bring up on silicon

Manager Silicon Design Engineering

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

10 to 15 years of experience in digital ASIC/SOC design verification
4 to 5 years manager experiences on ASIC/SOC design and verification
Experience working with a distributed team
Strong mentoring and coaching skills
Proven experience managing and leading engineering teams
Prior experience in optimizing performance (client, server, system, or embedded)
Strong system and software engineering background
Strong communications skills
Strong analytic and problem-solving skills
Must be a self-starter and self-motivated

Job Responsibility

Lead a high-performance engineering team
Form a team and nurture talents
Lead team, meet schedule commitments and provide strong support to various SoC
Collaborate with multi-functional leaders to drive AMD's success

Silicon Design Engineer

This position requires a deep understanding of device physics, components design...

Location

Taiwan , Hsinchu

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors degree in engineering or physical science, preferably with advanced degree (MS or PhD)
Working experience in baseband and RF component design and modeling
Proficiency in industry-standard EDA tools including Cadence Virtuoso, Spectre, and HSPICE
Strong background in SPICE modeling and QA for semiconductor devices
Familiar with foundry PDKs, parasitic extraction, and physical verification flows
Experience with EM simulation and modeling tools such as HFSS, EMX and ICCAP
Working knowledge of FinFET and GAA technologies at 3nm, 2nm, and beyond

Job Responsibility

Perform device characterization, SPICE modeling and simulation support to FPGA product design
Responsible for design, optimize, and validate baseband and RF components in advanced CMOS nodes
Perform schematic design and simulations using Cadence Virtuoso, Spectre, and HSPICE
Guide and review layout implementation to ensure optimal device performance and manufacturability
Analyze silicon measurement data and correlate with simulation models to enhance design accuracy
Conduct SPICE and EM modeling using tools such as ICCAP, HFSS or EMX
Explore and evaluate stacked-die and 3DIC technologies, including simulation, modeling and layout consideration for heterogeneous integration
Collaborate with foundry and internal teams to utilize and validate PDKs, perform parasitic extraction, and ensure physical verification compliance

Silicon Design Engineer

Be part of AMD IO IP team, joining IP design work on host controller IP for the ...

Location

Taiwan , Hsinchu; Taipei

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Expert in Static Timing Analysis, familiar with DC, PT, GCA, and commands, worked in timing closure tasks with high clock frequency
Expert in Verilog RTL design on large-scale digital IP
Good English communication, presentation, and documentation
Work is performed with limited supervision. Strong sense of task scheduling and delivering on time as predetermined milestones committed to the manager
Can solve complex, novel, and non-recurring problems
Major in EE, CS or related, Master Degree or Bachelor with solid working experiences

Job Responsibility

Takes part in host controller development based on architectural requirements for next-generation IO
Works on STA tasks such as defining clock architecture, creating SDC and exceptions, and analyzing timing reports
Works on RTL code development for IP blocks in Verilog HDL to ensure functionality is correct and reusable for multiple product lines
Deals with complex problems in both STA and RTL
Makes technical decisions
Coaches and mentors junior staff

Senior Photonics Design Engineer

As a Photonic Design Engineer at Salience Labs, you will play a crucial role in ...

Location

United Kingdom , Oxford

Salary:

Not provided

Salience Labs

Expiration Date

Until further notice

Requirements

Master’s degree in physics, photonics, electrical engineering, or optical engineering, with 5+ years of relevant experience (Ph.D. preferred)
Strong understanding of waveguide optics, integrated photonic devices, and semiconductor physics
Knowledge of silicon photonic components, with an understanding of their trade-offs
Experience in modelling and simulating integrated photonic devices, using both commercial software and analytical approaches
Excellent communication skills, critical thinking, and self-motivation

Job Responsibility

Designing and modelling passive and active silicon photonic devices and integrated photonic systems, including III-V's
Prototyping novel photonic components and architectures, designing suitable test structures, and validating experimental results against simulations
Using simulation and experimental data to evaluate device performance and guide engineering decisions
Working with the architecture team to develop system-level models for photonic integration
Supporting hardware and software teams to ensure alignment with system-level performance goals
Collaborating with component test engineers to design experiments and analyse results
Helping create and maintain the codebase for photonics component layout in GDS format
Partnering with manufacturing teams to optimise and transition designs into volume production
Contributing to intellectual property development, including filing patents for novel innovations

Physical Design Engineer

This role has been designed as ‘Hybrid’ with an expectation that you will work o...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

4+ years experience in ASIC physical design
Experience with block implementation, extraction, timing and or full-chip designs
Strong communication skills
Strong hands-on TCL/Perl development skills
Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
Track record of taping out complex chips on advanced process nodes

Job Responsibility

Responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow
Experienced in design automation
Understanding of Timing constraints, SI prevention, Power reduction

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Senior Manager Silicon Design Engineer

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

12-15 years full-time experience in IP hardware design
Proven experience managing and leading engineering teams
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
Clock domain crossing (CDC) tools
Detailed understanding of SoC design flows
Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
Outstanding interaction skills while communicating both written and verbally
Ability to work with multi-level functional teams across various geographies
Outstanding problem-solving and analytical skills

Job Responsibility

Lead a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies
Help bring to life cutting-edge designs, working closely with architecture, physical design, and product engineers to achieve first pass silicon success
Design of IP and subsystems with integration of AMD and other 3rd party IPs
Work collaboratively with other members of the IP team to support design verification, implementation, synthesis, constraints, static timing analysis, and delivery to SOC
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up

Photonics Engineering Post-doc

The Large Scale Integrated Photonics Lab (LSIP) at Hewlett-Packard Labs is curre...

Location

United States , Santa Barbara

Salary:

45.50 - 72.00 USD / Hour

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

PhD in Physics, Engineering or equivalent with experience in integrated photonics
Cleanroom experience in nanophotonic device fabrication
Hands-on experience with fabricating thin film lithium niobate photonic devices is preferred
Experience with the design of photonics devices
Testing of photonic devices
Squeezed-light generation and detection

Job Responsibility

Conduct innovative research in integrated photonics on various material platforms including silicon and lithium niobate thin films
Heterogeneous integration of III-V functional devices on integrated photonics platforms
Design, fabrication, and testing of devices for various applications including data communication, sensing and non-classical measurements

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Silicon Design Engineer

AMD

Location:
China , Shanghai

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
March 21, 2026

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