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Central DFX (CDFX) is a centralized ASIC design group within AMD's Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art APU computing, game console and GPU graphics products. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
Job Responsibility:
Understand Design-for-Test (DFT) architecture
Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem
Setup and execute design checks using both industry standard and in-house tools
Deliver Perl, python, TCL scripts that provide scalable solutions key to DFT implementation
Monitor CAD and/or IP regression results, debug failures and analyze coverage
Develop in-house automation, utilities, intranet web portal, AI/ML applications
Requirements:
Experience with Perl/Python/Shell scripting, C++, SQL
Experience with AI/ML application
Good object oriented programming skills
Digital circuits and VLSI knowledge
Strong problem solving skills
Good written and oral communication skills
Team player with strong interpersonal skills
Bachelors or Masters degree in computer engineering/Electrical Engineering