Silicon Design Engineer Job at AMD (Penang)

Job Description

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. As a member of the Central Engineering Group, you will help bring to life cutting-edge designs. The focus of this role is to plan, build, and execute the verification of new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) that is used in AMD’s product portfolio resulting in no bugs in the final design.

Job Responsibility

Candidate should be able to work independently on various DV task and providing technical guidance to DV team
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Requirements

Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Strong background with UVM, Verilog, System Verilog, C, and C++
Developing UVM based verification frameworks and testbenches, processes and flows
Automating workflows in a distributed compute environment
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language (SVA, UVM scoreboard)
Good working knowledge of SystemC and TLM with some related experience
Over 7 yrs of digital IP verification with SV/UVM/formal verification or new methodology of the industry
Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

USB,UFS,Ethernet,PCIE,AXI knowledge
Exposure to power aware simulations
Scripting language experience: Perl, Ruby, Makefile, shell
Exposure to leadership or mentorship

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Silicon Design Engineer

Job Description

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Requirements

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