Signal Integrity Testing Engineer Job at Aptiv plc (Nantong)

Signal Integrity & Power Integrity Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great pro...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience in packaging, connector and board design for power & signal integrity
Experience in electrical modeling EDA tools such as Cadence, Ansys HFSS, SIwave, ADS, etc.
Experience in high-speed digital signaling interfaces such as PCIE, USB, GDDR and DDR
Experience in SI/PI simulation and processing of s-parameters
Knowledge in silicon interposer and optical interconnects simulations
Knowledge in analog characterization, electromagnetic theory and digital circuit analysis
Experience in test board design, fixtures and de-embedding methodologies is a plus
Experience in measurement tools VNA, TDR and high speed oscilloscope is a plus
Ability to collaborate and work across different functional teams and different sites
Self-driven and can work independently

Job Responsibility

Electrical design and characterization of high-speed signaling and power delivery networks in AMD products covering package, connector and board
Communicate effectively and work in close collaboration with others in AMD as well as with AMD’s customers to ensure optimal engineering design decisions and efficient problem solving

Fulltime

Signal Integrity / Power Integrity Engineer - Wearables

Signal Integrity and Power Integrity (SIPI) Engineers at Meta design, analyze, a...

Location

United States , Sunnyvale

Salary:

173000.00 - 245000.00 USD / Year

Graduate Trainee - Product Development Engineer (Signal Integrity)

As Signal Integrity Design Engineer, you will be responsible for SI specificatio...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor's or Master's in electrical engineering, computer engineering, or comparable disciplines
Electromagnetic modeling of 3-D structures including vias, connectors, sockets
System-level signal integrity simulations of DDR5 memory bus
System-level signal integrity simulations of high-speed SERDES links such as USB-4, PCIe5, xGMI/CXL
Expertise in analog simulation with Seasim, S2eye, Hspice, ADS, ANSYS, or other toolsets
Expertise in 3-D modeling with ANSYS HFSS/Q3D and 2.5-D with ANSYS SIWAVE
Expertise with DSO, TDR, VNA, ParBERT measurement tools/techniques

Job Responsibility

Work closely with cross-functional team and internal working group on current and next gen Server's platform in meeting signal integrity in HVM solution space
Electromagnetic modeling of 3-D structures including vias, connectors, sockets
Verify and correlate post-silicon measurement against spec and collaborate fixes if needed to feedback on the next derivation silicon
Collaborate with working group leads for signal measurement test plans and review of measurement results
Deliver channel optimization (board and package), model creation and verification and simulate the overall performance to meet the channel performance
Be part of the team to develop and enhance next generation product and methodology
Board/system-level power delivery network AC+DC simulation for low-voltage/ high-current supplies
Work with external and internal IP providers to ensure IPs performance and their proper functionality in our products
System-level signal integrity simulations of future DDR5 memory bus including silicon IO, package, and board
System-level signal integrity simulations of future high-speed SERDES links such as USB-4, PCIe5, xGMI/CXL, etc. including silicon IO, package, and board

Fulltime

Signal Integrity Engineer, Intern

Meta is seeking a platform Signal Integrity (SI) intern to join our Infra HDRTP ...

Location

United States , Menlo Park

Salary:

6688.00 - 11467.00 USD / Month

Signal Integrity Engineer

OpenAI’s Hardware organization develops silicon and system-level solutions desig...

Location

United States , San Francisco

Salary:

225000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

At least 10 years of industry experience
Experience design hardware system and SerDes testing for data center applications
Experience and good knowledge of system design experience in the SI areas, from chip, SerDes, board, rack level
Experience with PCB, connector and cable design

Job Responsibility

Lead system signal integrity (SI) design for AI supercomputer product in the data center application
Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies
Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity
Perform simulation and modeling to identify and troubleshoot signal integrity issues
Lead system interconnect design, bring up and qualification
As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

Senior Hardware Signal & Power Integrity Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Santa Clara

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience
OR equivalent experience
3+ years experience in SI & PI analysis of complex multilayer PCBs & backplanes
3+ years experience in simulation/correlation using 2D/2.5D/3D simulation tools
3+ years experience using Keysight ADS, Ansys HFSS, Cadence Sigrity, PowerSI, Ansys SIwave, Hspice, Matlab
3+ years of technical knowledge & working experience with PCIe, DDR4/DDR5 (Memory, PHY, Controller), Ethernet (MAC/PHY), NRZ & PAM4 Serdes, I2C, SPI, MDIO..Etc
3+ years of hands-on experience in using lab/debug tools (e.g., High-speed Oscilloscopes, TDR, VNA, Bertscope, and Spectrum Analyzer)
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role

Job Responsibility

Perform system level signal integrity simulations of high-speed interfaces, create simulation models and develop simulation methodology for the designs
Perform power integrity simulations including AC and DC analysis
Develop serdes channel simulation models and correlate to test structures
Support stackup creation, develop layout/SI checklists, work with board engineers and layout designers to implement all SI rules
Perform SI DVT measurements on boards and correlate measurements with simulation results
Work cross-functionally with the other teams to plan and design the SI/PI needs for the system

Fulltime

Senior Signal and Power Integrity Engineer

At Cisco, Bangalore, the Common Hardware Group (CHG) architects, designs, builds...

Location

India , Bangalore

Salary:

Not provided

Duo Security

Expiration Date

Until further notice

Requirements

Bachelor's or Master’s Degree in Electrical Engineering
6+ yrs of demonstrated ability in hardware design with emphasis on Signal and Power Integrity
Hands on exposure to lab measurements including real-time scope, sampling scope, Spectrum analyzer, VNA & TDR
Good understanding of EM and transmission line concepts, timing, jitter, crosstalk, noise, channel modeling, channel equalization techniques, power delivery & decoupling
Experience with 56G PAM4, 25G & 10G NRZ Serdes technologies, and DDR - simulation, bring up, debug, measurements, and optimization
Thorough knowledge of PCB stack-up design - standard processes, performance vis-à-vis PCB materials, surface finishes, vendor capabilities, and manufacturing trade-offs
Proficiency with simulation and analysis tools like ADS, HFSS, HSPICE, Cadence Allegro, PowerSI, MATLAB, and Hyperlynx
Excellent oral and written communication skills and capability to present concepts, analysis, and updates to larger teams and forums

Job Responsibility

Be responsible for delivering system-level signal and power integrity solutions for large sophisticated high-speed systems, boards & packages
Develop SI rules, review design implementation, build test plans, and document characterization & measurement reports
Improve & optimize design margins through interconnect, timing and crosstalk analysis, 3D EM & channel simulations for high-speed designs
Design & characterize test structures & channel models to correlate simulations with measurements for Serdes and interconnects
Collaborate with multi-functional teams - HW, PCB Layout, SW, MFG, ASIC
Be responsible for electrical characterization and verification of Transmitter/Receiver SERDES settings to meet the industry standards and internal Cisco requirements

Senior Hardware Engineer - Signal Delivery

The Innovation Lab is an advanced R&D team that is part of the Semiconductor Tes...

Location

United States , North Reading

Salary:

175300.00 - 280600.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or related field
Minimum 7 years of experience in signal integrity or high-speed hardware design
Proven experience with signal delivery in advanced semiconductor systems
Strong working knowledge interconnect standards
Experience working with microbump technology and its impact on signal integrity
Familiarity with fine pitch probing techniques and associated challenges
Proficiency in simulation tools such as Ansys HFSS, SIwave, ADS, or equivalent
Experience with PCB layout tools and design for signal integrity
Familiarity with lab equipment for signal validation (oscilloscopes, TDR, VNA)
Strong analytical and problem-solving skills

Job Responsibility

Lead the design and analysis of high-speed signal delivery systems supporting high speed industry data interfaces such as PCIe, UCIe, etc.
Develop simulation models and perform signal integrity analysis to ensure robust performance across various operating conditions
Collaborate with cross-functional teams including packaging, PCB layout, and silicon design to optimize signal paths and microbump connections
Build and validate prototypes to test signal delivery performance and compliance of system probe card interfaces including microbump and fine pitch probing specifications
Support product development from concept through production, ensuring signal integrity and reliability
Ensure compliance with industry standards and internal quality metrics
Drive PCB design efforts involving very large panels, high layer count sequential builds, and fine pitch sequential lamination
Lead development of ultra-fine pitch MLO (Multi-Layer Organic) substrates with embedded active and passive components
Coordinate and manage cross-site, global engineering teams to ensure alignment and execution across time zones
Provide clear, data-driven risk assessments and mitigation strategies to management and stakeholders

What we offer

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more
This job is eligible for discretionary bonus(es) based on financial performance

Fulltime

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Signal Integrity Testing Engineer

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