Short Term 2026 Hardware Design Engineering Intern/Co-Op

• Collaborate with Design Engineers on the physical design verification and physical implementation for some of our ASIC
• Work on Memory interface simulation work eg. GDDR7, HBM, UCIE
• Work on Discreate and Embedded hardware products and chip to chip interconnect
• Actively participate in RTL design in Verilog
• Synthesis with timing driven placement and design for power (DFP)
• Floor planning, Power distribution, Clock distribution, Block/Chip Place & Route, EM/IR analysis, Timing closure, Static Timing Analysis
• analysis of logical equivalent check, RTL clocking analysis, static power analysis, and design for test (DFT)
• Build test libraries and models by using advanced verification languages such as System Verilog, UVM and C++

• Currently enrolled in a Canada based University into a Bachelor's degree program majoring in Electrical engineering or Computer engineering or a related field
• Strong semiconductor device physics knowledge
• Digital /Logic circuits and VLSI
• Verilog or VHDL hardware description languages
• Exposure to UVM methodologies
• Scripting languages (e.g. Python, Perl, TCL, Ruby), Shell / UNIX scripting, C/C++, MATLAB
• Interest or experience in Machine Learning
• ASIC design
• Knowledge of Ruby on Rails and MySQL
• Linux/Unix environment
• Physical design (PD) process
• Chip level design/integration activities and DFT

AMD benefits at a glance