Server Performance Architect

• Develop and execute performance verification plans targeting IPC, latency, throughput, and power efficiency
• Capability to debug performance outliers through Performance Monitoring Counters (PMC)
• Drive correlation between RTL and performance models, ensuring architectural intent is met
• Analyze performance bottlenecks using simulation, emulation, and silicon data
• Build and maintain scalable, modular performance verification infrastructure
• Provide emulation-based performance setup and debug, enabling early performance validation
• Integrate performance regression, profiling, and analysis flows using industry-standard and custom tools
• Collaborate with compiler and OS teams to ensure software stack alignment with hardware performance goals
• Drive the development of AI/ML-based infrastructure to automate performance analysis, anomaly detection, and efficiency improvements
• Leverage data-driven techniques to optimize verification coverage and reduce debug cycles
• Partner with x86 architecture, RTL design, physical design, and software teams to ensure performance targets are met
• Influence design decisions through data-backed performance insights
• Stay current with trends in CPU architecture, performance modeling, and verification technologies
• Evaluate and adopt emerging tools and techniques to maintain a competitive edge

• Should have executed Emulation based functional and performance verification for multimillion gate SoC designs
• Should have strong exposure to RTL coding and SOC bring-up debug
• Exceptional foundation in systems architecture, cutting across CPU, memory, storage and I/O subsystems
• Experience with hardware performance counter monitoring tools
• Should have exposure to performance profiling tools, preferably x86 based (e.g. linux perf, Windows perfmon)
• MS/PhD in Computer Engineering / relevant coursework / thesis
• Excellent communication skills (verbal, written, and presentation)
• > 4 years relevant industry experience

• Deep knowledge of modern out-of-order CPU cores, memory subsystems, and performance modeling
• Familiarity with performance benchmarks like SPEC CPU
• Experience with ML/AI techniques/frameworks for performance triage, infrastructure automation and prediction
• Exposure to high-performance computing (HPC), virtualization, or server-class CPUs
• Background in hardware/software co-design and performance-aware compiler optimizations
• Familiarity with pre-silicon and post-silicon debug methodologies

Benefits offered are described: AMD benefits at a glance