Serdes Systems Validation Engineer Job at BLUESTREAM PEOPLE (Hampshire)

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Senior SerDes Verification Engineer

AMD is seeking a talented SerDes Verification Engineer to work on verifying and ...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience in SerDes verification or high-speed communication verification
Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools
Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols
Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams
Solid understanding of SerDes architectures, link training, and equalization
Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance)
Familiarity with hardware description languages (HDL) like VHDL or Verilog
Strong analytical, problem-solving, and communication skills
Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification
Understanding of UCIe protocol and its role in chiplet-to-chiplet communication

Job Responsibility

Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements
Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL)
Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks
Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics
Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols
Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations
Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes
Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing
Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies

Fulltime

Software Engineer Sr Staff - Platforms Developer

Designs, develops, troubleshoots and debugs software programs for software enhan...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in computer science, electronics, telecommunication engineering, or a related discipline
14 to 19 years of experience in networking and system software development
Proficiency in C and C++ programming
Familiarity with data structures and system debugging techniques
Expertise in Host Complex, System Peripherals & Drivers: CPU complex (x86)
PCIe, SPI, I2C, MDIO
FPGA, CPLD, Flash Drivers
Expertise in Ethernet Interfaces (ranging from 1Gig to 400G+, including 800G, 1.6T), MacSec, Timing, Optics (SFP, QSFP, QDD, OSFP)
Expertise in High-speed packet forwarding with network processors, PHYs, and SerDes
Cloud Architectures

Job Responsibility

Collaborate with product managers, architects, and other engineers to define software requirements and specifications
Design, implement, and maintain networking and system software components using C and C++ programming languages
Conduct object-oriented analysis and design to ensure robust and scalable solutions
Debug complex system-level issues, leveraging your deep understanding of fundamental OS concepts (especially in Linux or similar operating systems)
Participate in hardware and system-level design discussions, ensuring carrier-class software development
Work with Linux device drivers, system bring-up, and the Linux kernel
Navigate large codebases effectively
Apply strong technical, analytical, and problem-solving skills to enhance software performance and resilience
Utilize scripting technologies and modern DevOps practices
Collaborate with cross-functional teams, including networking, embedded platform software, and hardware experts

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Senior Silicon Validation Engineer

HPE is seeking a Senior Silicon Validation Engineer to help validate the functio...

Location

United States , Ft. Collins

Salary:

142000.00 - 270000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

May 28, 2026

Requirements

Bachelor’s or master’s degree in electrical engineering, computer engineering, computer science or equivalent
6-10+ years of experience in VLSI Validation, verification, or design, including experience leading teams or complex projects
Senior level proficiency in object-oriented Python programming
Senior level proficiency in Linux command line, Verilog hardware description language, electronic design automation (EDA)
Senior level experience in ASIC Silicon Validation and testing is required
Senior level knowledge of industry standard networking protocols is required. (200G/400G/800G+ Ethernet, 50G/100G/200G+ SERDES (Die to Die as well as long reach))
Executive written and verbal communication skills
mastery in English
Must hold U.S. citizenship, U.S. lawful permanent resident/Green Card status

Job Responsibility

Oversees full chip-level validation, utilizing emulators and developing tests that run at the operating system level to assess both HPE Slingshot and industry standard networking protocols
Provides technical leadership for the HPE Slingshot Silicon Validation engineering team, responsible for all stages of ASIC validation for Network Interface Cards (NIC) and Switch hardware
Provides technical leadership and guidance to cross-organization projects and activities
Owns the validation strategy and risk management for major projects
Drives innovation and integration of new technologies and methodologies into Silicon Validation projects and activities
Provides input on the selection and development of future technical leaders
Mentors and develops less experienced staff members, setting an example of innovation and excellence in Silicon Validation
Represents the organization in external engagements, including partner collaborations and industry forums
Collaborates and communicates with management and internal partners regarding validation status, project progress, and issue resolution

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Senior R&D Hardware Engineer

As a Senior Hardware Design Engineer, you will be part of a dynamic and highly s...

Location

United States , Roseville

Salary:

115500.00 - 266000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

10+ years of experience in hardware system design and/or high-speed board designs
Proficient with Cadence schematic and PCB design tools like Concept, Orcad and Allegro
Strong technical foundation in high-speed (Gbps) physical design, signal integrity principles and power distribution techniques
Hands-on experience with lab design verification activities and troubleshooting complex system issues relating EMI/EMC, reliability and serdes I/O
Knowledge of programming languages such as Python, Perl and Matlab
Must possess a bachelor’s or master’s degree in electrical engineering or related fields

Job Responsibility

Hardware specification, PCA circuit design, component selection, system bring-up, board debug and platform verification
Lead a team or work independently on complex board designs and solving issues
Collaborate with a multi-sited R&D team to integrate your deliverables toward a successful release of new products into production
Conduct feasibility, design margin and validation analysis, and empirical testing on new and modified designs
Contribute to new innovation to solve emerging technology requirements for Enterprise networking products

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Senior Hardware Engineer

Piper Companies is seeking a Senior Hardware Engineer to lead the full developme...

Location

United States , Saratoga

Salary:

210000.00 - 260000.00 USD / Year

Piper Companies

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Electrical Engineering or Computer Engineering required
Master’s degree a plus
10+ years of system‑level hardware development experience in server, compute, or networking products
Strong background in high‑speed interfaces including Ethernet, PCIe, SerDes, and optical modules
Deep understanding of high‑speed design principles, as well as signal‑ and power‑integrity best practices
Working knowledge of FPGA development flows, power system design, and clocking architectures
Solid grasp of system‑level hardware concepts, including chassis design, connectors, cabling, and thermal management
Proven track record delivering production‑quality hardware using industry‑standard development and release processes

Job Responsibility

Overseeing hardware design execution, including schematic development, PCB layout, and design reviews
Managing all Signal Integrity (SI) and Power Integrity (PI) analysis activities for high‑speed systems
Developing technology de‑risking plans through supplier assessments and early prototype cycles
Owning test strategy and execution across Bring‑Up, EDVT, MDVT, and EMI/EMC validation
Guiding systems from early prototype builds through full production while meeting quality, cost, schedule, and budget goals
Troubleshoot and resolve hardware-related issues, providing technical support to internal and external stakeholders

What we offer

Comprehensive benefits package including Medical, Dental, Vision, 401k, PTO, holidays, and sick leave as required by law

Fulltime

Principal Quantum Systems Digital Design Engineer

Microsoft is the world’s center of expertise on topological quantum computing. W...

Location

United States , Redmond

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Electrical/Computer Engineering, or related field AND 3+ years experience in industry or in a research and development environment
OR Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience
6+ years programming experience in related programming languages
6+ years experience in a collaborative environment
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development
Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval

Job Responsibility

Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade‑offs and power/thermal considerations
Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning
Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance
Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams
contribute to system‑level design reviews
Verification and validation: develop simulation and constrained‑random tests (SV/UVM or equivalent), build on‑board diagnostics (ILA/ChipScope), and execute lab bring‑up with scopes, VNAs, LA/SC, and RF instruments
Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign‑off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD
Quality & documentation: produce clear design docs, interface specs, and bring‑up guides
participate in rigorous code/design reviews and post‑silicon/post‑fabrication retros

Fulltime

Analog IC Design Architect

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

United States , Boxborough

Salary:

136000.00 - 204000.00 USD / Year

Synopsis Engineering

Expiration Date

Until further notice

Requirements

>15 years experience in PHY analog design, including pre-silicon and post-silicon validation
Strong knowledge of physical IP such as SERDES, DDR/HBM or Die to Die IO Interface
Expertise in design trade-offs, flows, and methodologies
Skilled in generating and supporting documentation through written specifications, and communicating those specifications within a design team and to external customers
Able to work across a multi-site team to communicate ideas, understand problems, and find solutions to create a leading-edge design
Skilled in troubleshooting and debug of mixed-signal interfaces
Proficiency in using industry-standard design tools and software
Excellent problem-solving skills and the ability to make strategic decisions
Experience in leading and driving technical solutions across organization, across function, across geography
The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams

Job Responsibility

Driving the development of world class high-performance D2D IPs to enable customer chiplet bases system design win across industries
Designing, developing, and evaluating PHY analog components for pre-silicon and post-silicon validation
Driving next gen Die to Die IP architecture definition and path finding
Customizing PHY designs to meet specific client requirements and performance criteria
Performing design trade-offs to optimize power, performance, and area (PPA)
Developing and implementing design flows and methodologies to streamline the design process
Collaborating with cross-functional teams to ensure seamless integration of analog components with digital systems
Providing technical guidance and mentorship to junior engineers and team members

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Networking Operating System Firmware Engineer

We’re seeking a Networking Operating System Firmware Engineer to help bootstrap ...

Location

United States , San Francisco

Salary:

266000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

Proven experience working with SONiC or comparable NOS stacks (FBOSS, Cumulus Linux, Arista EOS, Junos PFE-level integration, etc.)
Experience with updating OpenConfig gNMI interfaces and YANG data models
Strong background in Linux kernel, network device drivers, and low-level OS internals
Experience integrating Broadcom / Marvell / NVIDIA / Intel ASIC SDKs and SAI implementations
Proficiency in C, C++ and Python
Deep understanding of L2/L3 forwarding, ECMP, RoCE, BGP, QoS, PFC, buffer tuning, and telemetry
Hands-on experience with hardware platform bring-up and board-level debugging
Familiarity with CI/CD pipelines, distributed config/state management, and large-scale automation
Strong cross-functional problem solving in high-performance, distributed environments
Ability to lead teams to deliver a project end to end

Job Responsibility

Design, develop, and maintain custom SONiC NOS images for large-scale bleeding-edge AI fabrics
Integrate and configure Linux kernel components, device drivers, switch ASIC SDKs, and SAI layers
Bring up new switch platforms (thermal/fan control, power monitoring, transceiver management, watchdogs, OSFP CMIS, LEDs, CPLDs, etc.)
Extend and customize SONiC services for routing, telemetry, control-plane state, and distributed automation
Work with hardware teams to validate ASIC configurations, link bring-up, SerDes tuning, buffer profiles, and performance baselines
Evaluate switch silicon SDK releases, track vendor deliverables, and define platform requirements with vendors and ASIC partners
Debug complex issues spanning kernel, platform drivers, SONiC dockers, routing agents, orchestration services, hardware signals, and network topology
Integrate switches into fleet-wide monitoring, remote diagnostics, telemetry pipelines, and automated lifecycle workflows
Develop robust CI/build pipelines for reproducible NOS builds and controlled rollout across the fleet
Support factory bring-up and qualification all the way through mass deployment

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

Serdes Systems Validation Engineer

BLUESTREAM PEOPLE

Location:
United Kingdom , Hampshire

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
December 06, 2025

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Location:United Kingdom , Hampshire

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Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:December 06, 2025

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Job Posted:
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