Serdes Systems Validation Engineer Job at BLUESTREAM PEOPLE (Hampshire)

Senior SerDes Verification Engineer

AMD is seeking a talented SerDes Verification Engineer to work on verifying and ...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience in SerDes verification or high-speed communication verification
Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools
Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols
Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams
Solid understanding of SerDes architectures, link training, and equalization
Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance)
Familiarity with hardware description languages (HDL) like VHDL or Verilog
Strong analytical, problem-solving, and communication skills
Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification
Understanding of UCIe protocol and its role in chiplet-to-chiplet communication

Job Responsibility

Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements
Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL)
Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks
Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics
Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols
Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations
Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes
Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing
Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies

Fulltime

Lead SerDes Technical Marketing Engineer

We are seeking a highly motivated Technical Marketing Engineer (TME) to drive cu...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience in SerDes, signal integrity, high-speed digital design, or related areas
Strong understanding of high-speed protocols such as PCIe, Ethernet, CXL, USB, DisplayPort, and PAM4-based interfaces
Experience with SerDes concepts including CDR, CTLE, DFE, FEC, jitter analysis, and link optimization
Familiarity with high-speed PCB design and system-level SI considerations
Hands-on experience with lab equipment such as oscilloscopes, VNAs, and SerDes debug/evaluation tools
Strong written, verbal, and presentation skills with the ability to communicate complex technical concepts clearly
Proven ability to work cross-functionally and support customer-focused technical initiatives

Job Responsibility

Serve as a technical expert for high-speed SerDes technologies and system-level interface performance
Support customer engagements, design reviews, technical presentations, and system optimization discussions
Develop technical collateral including presentations, application notes, whitepapers, and training material
Collaborate with engineering, product management, and sales teams to align customer requirements with product capabilities
Conduct technical training sessions for internal teams and customers
Support benchmarking, channel analysis, SI evaluation, and performance validation activities
Represent the company at customer meetings, webinars, conferences, and industry events
Stay current with emerging SerDes technologies, protocols, and market trends

What we offer

Benefits offered are described: AMD benefits at a glance

Fulltime

Principal FPGA Design Engineer - 4G/5G Radio Systems

Are you a FPGA Design Engineer looking for a new opportunity? Are you looking fo...

Location

Canada , Kanata

Salary:

62.19 - 72.43 USD / Hour

Randstad

Expiration Date

June 29, 2026

Requirements

7+ Years of RTL Expertise: Proven track record in high-complexity FPGA design, specifically using SystemVerilog or Verilog. (Note: Candidate must be willing to work exclusively in a non-VHDL environment).
Altera/Intel Toolchain: Mastery of Quartus Prime for synthesis, place-and-route, and timing closure on high-density FPGAs.
DSP Modeling: Proficiency in MATLAB and Simulink for algorithmic modeling and fixed-point simulation prior to RTL implementation.
Protocol Mastery: Deep expertise in AXI (AXI4-Stream, AXI4-Lite) and Ethernet (10G/25G/100G) protocol implementation.
High Speed Interfaces: Practical experience with JESD204B/C, PCIe, and multi-gigabit SERDES transceivers.
Synchronization: Understanding of timing and synchronization protocols, such as PTP (IEEE 1588) and SyncE.
Wireless Infrastructure: Direct experience developing Radio Units (RU) or Massive MIMO systems.
Industry Standards: Functional knowledge of 3GPP physical layer specifications and O-RAN (Open RAN) Fronthaul interfaces (eCPRI/CPRI).
Signal Processing: Experience implementing Digital Up/Down Conversion (DUC/DDC), Crest Factor Reduction (CFR), or Digital Pre-Distortion (DPD) in hardware.
Advanced Verification: Experience with UVM (Universal Verification Methodology) and constrained-random testing to ensure 'first-time-right' silicon/FPGA bitstreams.

Job Responsibility

Define System Requirements: Translate high-level customer needs and 3GPP/O-RAN standards into detailed functional specifications for the entire FPGA ecosystem.
Drive 5G Roadmap: Architect FPGA IP specifically for 4G/5G Radio Units, ensuring designs align with industry trends and long-term organizational strategy.
Strategic Design Choices: Set the standard for product excellence by selecting optimal components and design methodologies to meet aggressive cost and performance targets.
High-Complexity RTL Development: Lead the implementation of complex logic blocks using SystemVerilog, focusing on high-speed Ethernet and AXI protocol integration.
Model-Based Design: Utilize MATLAB and Simulink to model signal processing algorithms before translating them into hardware-efficient RTL.
Ensure Design Integrity: Oversee the full validation lifecycle, from UVM-based simulation to hands-on system-level testing and timing closure using Altera Quartus.
Hardware-Software Synergy: Partner closely with software and RF teams to ensure seamless interoperability between hardware logic and low-level software drivers.
Technical Authority: Act as the primary consultant on critical, high-impact projects, providing 'whiteboard-level' solutions to unusually complex engineering hurdles.
Team Mentorship: Provide technical guidance to junior engineers, fostering a culture of best practices in RTL coding and version control (Git).
Executive Communication: Bridge the gap between engineering and management by communicating project progress, risks, and technical visions to senior leadership.

Fulltime

Principal Quantum Systems Digital Design Engineer

Microsoft is the world’s center of expertise on topological quantum computing. W...

Location

United States , Redmond

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Electrical/Computer Engineering, or related field AND 3+ years experience in industry or in a research and development environment
OR Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience
6+ years programming experience in related programming languages
6+ years experience in a collaborative environment
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development
Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval

Job Responsibility

Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade‑offs and power/thermal considerations
Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning
Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance
Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams
contribute to system‑level design reviews
Verification and validation: develop simulation and constrained‑random tests (SV/UVM or equivalent), build on‑board diagnostics (ILA/ChipScope), and execute lab bring‑up with scopes, VNAs, LA/SC, and RF instruments
Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign‑off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD
Quality & documentation: produce clear design docs, interface specs, and bring‑up guides
participate in rigorous code/design reviews and post‑silicon/post‑fabrication retros

Fulltime

New

Senior Opto-Electronics Engineer

At Microsoft Research, we are shaping the future of AI infrastructure by pursuin...

Location

United Kingdom , Cambridge

Salary:

73800.00 - 121300.00 GBP / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

PhD in Electrical Engineering, Physics, Photonics, Optical Engineering, or a related field
Strong background in signal processing for communication systems, analog/mixed-signal circuit design, Integrated circuit (ASIC/CMOS) design
Proven industry experience in the design and delivery of optoelectronic systems and integrated circuits
Experience with optical transceivers, connectivity systems, or advanced optical I/O architectures
Hands-on experience with lab measurements and characterisation (e.g., RF measurements, eye diagrams, BER testing)
Strong experience in end-to-end link modelling and simulation, including circuit-level (SPICE) and system-level (Python-based) analysis
Ability to operate effectively in a multi-disciplinary environment
Excellent communication skills in English, both written and spoken, including the skill to clearly communicate technical results and justify assumptions to diverse technical audiences

Job Responsibility

Design and develop high-speed optoelectronic systems, including optical transceivers and connectivity chip architectures
Perform system-level modelling and co-simulation of electronic, photonic, and packaging effects
Co-design electrical and optical interfaces, ensuring signal integrity, bandwidth efficiency, and power optimization
Develop and implement high-speed interface architectures, spanning host-side SerDes and parallel low-speed optical links, including analog equalization, clocking strategies, and link-level optimization
Design and simulate analog and mixed-signal CMOS circuits (e.g., drivers, TIAs, PLLs)
Contribute to ASIC and IC design flows, including architecture definition, modelling, and verification
Collaborate with internal teams and external partners to support tape-outs, bring-up, and validation of silicon and photonic devices
Analyze experimental data, align it with simulation outcomes, and drive iterative design improvements to meet performance targets

What we offer

Benefits and other compensation

Fulltime

Serdes Analog Mixed-Signal Design Expert

AMD Serdes Technology Group develops high-performance electrical and optical tra...

Location

United States , San Jose

Salary:

216000.00 - 324000.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

PhD in Electrical Engineering or a related field or MS with relevant industrial experience in optical and/or electrical transceiver design
experience designing 200G+ CMOS transceivers, with a deep understanding of high-speed electrical and/or optical interface requirements
demonstrated proficiency in hands-on circuit optimizations, including tuning for power, performance, and area at both block and system levels
proven track record in silicon productization—from initial design through to bring-up, validation, and successful ramp to mass production

Job Responsibility

Own performance-critical analog mixed-signal circuit blocks used in Serdes, such as high-speed data converters (DAC and ADC), clocking (reference clock, PLL, clock dividers, muxes, buffers, regulators, multi-phase clock generators, error detection and correction), and analog front-end circuits (pad matching networks, ESD, CTLE, linear amplifier)
define circuit-driven micro-architectures of Tx and Rx subsystems and drive sub-block level specs
own power, performance, area, and jitter budgets of analog design blocks
mentor sub-block owners and conduct peer reviews of design and verification results
work with pre-tapeout verification and post-silicon validation teams to bring up silicon and analyze silicon results

Fulltime

Fpga Developer / Fpga Design Engineer (4g/5g Radio – Datapath / Ru Fpga Design)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

Hands-on DSP (Digital Signal Processing) expertise including FFT, Beamforming, and Digital Filter implementation
Strong MATLAB / Simulink experience
SystemVerilog and RTL design experience for complex FPGA-based systems
Experience developing FPGA IP and architectures for 4G/5G Radio Units
Knowledge of AXI and Ethernet protocols
Experience with FPGA development tools including Altera Quartus and MATLAB/Simulink
Exposure to model-based design methodologies and FPGA implementation workflows
Understanding of wireless communications, 4G/5G radio architecture, O-RAN, LTE, eCPRI, CPRI, and PTP protocols is desirable but not mandatory
Experience optimizing FPGA resource utilization, timing closure, and high-performance datapath processing
Knowledge of high-speed interfaces such as Ethernet, PCIe, JESD204B/C, AXI, and SERDES technologies

Fpga Manager

As an FPGA Engineering Manager, you will serve as a formal people manager and te...

Location

United States , North Reading

Salary:

192300.00 - 307600.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

10+ years of experience in FPGA design, implementation, and verification
Strong proficiency in Verilog for FPGA synthesis
Hands-on experience with AMD (Xilinx) and/or Intel (Altera) FPGA toolchains, including IP configuration and timing constraint development
Proven design experience with digital and mixed-signal interfaces such as high-speed serial interfaces (e.g., PCIe, SerDes), memory interfaces (DDR), ADCs/DACs, and control and communication protocols (AXI4, SPI, I2C, USB)
Experience building verification environments, simulations, and testbenches for new FPGA features
Ability to read and interpret schematics and understand digital hardware design
Experience validating FPGA functionality on real hardware platforms
Strong communication skills and ability to collaborate across disciplines and cultures
Driven, self-starter mindset with a bias for action and strong ownership from problem definition through delivery
Demonstrated ability to build and lead teams—recruiting, onboarding, mentoring, and creating an environment where engineers can do their best work

Job Responsibility

Mentor and coach engineers, providing technical guidance, code/design reviews, and support for professional development
Manage and lead a team of FPGA engineers (direct reports): set goals and priorities, delegate effectively, run regular 1:1s, and ensure on-time, high-quality delivery
Manage a verification team, including external partners, to ensure clear scope, priorities, quality expectations, and execution cadence
Develop and implement FPGA designs for advanced power semiconductor test systems
Collaborate with cross-functional teams to define FPGA requirements and write detailed specifications aligned with product and system-level needs
Drive FPGA development from architecture and IP selection through implementation, verification, and release
Contribute to FPGA-related hardware design decisions including device selection, pinout planning, and high-speed interfaces
Support firmware and software teams during board bring-up, system integration, and factory readiness
Perform hands-on debugging and validation using lab equipment such as logic analyzers, oscilloscopes, and JTAG tools
Help evolve FPGA architectures to support high-throughput, deterministic, and scalable power test solutions for emerging workloads including AI and wide-bandgap devices

What we offer

Medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs
discretionary bonus based on financial performance

Fulltime

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Serdes Systems Validation Engineer

Job Description

Job Responsibility

Requirements

What we offer

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