SerDes PHY Engineer Job at AMD (Austin)

Hardware Engineer 3

Location

United States , Sunnyvale

Salary:

135500.00 - 275000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's degree or higher in Electrical, Electronics, or Computer Engineering
8+ years of hardware design, debug and testing experience at the board and system level
Expertise in debugging hardware problems using oscilloscopes, logic analyzers, and specialized networking test equipment such as IXIA/Spirent traffic analyzers, PCI analyzers, and in-circuit emulators
PCB design experience including schematic capture, PCB layout and routing
Familiarity with Cadence System Design tool suite
Knowledge of networking hardware and associated components and interfaces such as switch ASICs, PHY, SerDes, CPU subsystems, optics, high-speed serial links, PoE, PCIe, NVMe, SATA, I2C, and USB
Expertise in high speed circuit design and debug
Familiarity with signal and power integrity concepts and associated test and simulation tools
Ability to manage multiple concurrent priorities and make progress
Able to manage hardware debug and design projects and driving them to closure

Job Responsibility

Lead failure analysis for critical hardware issues reported from field and factory
Determine and document root cause and corrective actions (RCCA)
Extract and share 'Lessons Learned' from HW Sustaining failure analysis and share with appropriate Juniper teams to drive hardware quality improvement
Collaborate with other Engineering and Manufacturing / Operations teams to drive corrective actions and hardware quality improvements
Work with Customer Support teams to understand and address customer hardware concerns
Analyze hardware quality metrics and Repair Center findings to identify failure trends requiring investigation
Provide technical leadership into multi-sourcing and change management activities on shipping products
Review hardware test reports for new products prior to product release
Identify any quality concerns and work with the design teams to resolve
Mentor and guide junior members, foster a collaborative environment, and encourage curiosity and knowledge sharing

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

AI Scale-up Switch System Design Engineer

We are looking for a hands-on, technically sharp system design engineer to join ...

Location

United States , Secaucus

Salary:

117200.00 - 175800.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Hands-on experience in hardware bring-up, platform validation, or high-speed networking silicon characterization
Experience with high-speed switch ASICs (Broadcom TH6/Tomahawk series preferred) and familiarity with Broadcom's SDK/DAPI frameworks
Deep understanding of high-speed Ethernet standards (400GbE, 800GbE) including AN/LT (IEEE 802.3), RS-FEC / KP4-FEC, and PAM4 SerDes technology
Hands-on experience with PRBS testing, BER measurement, eye diagram analysis, and Snake/loopback traffic validation methodologies
Familiarity with LinkCAT or equivalent PHY/link characterization tools
Experience with server management protocols: IPMI, Redfish/OpenBMC, KCS, IPMB, and PLDM for out-of-band control and telemetry
Proficiency in Python for test automation, log parsing, and data analysis
Strong debugging skills — comfortable working across hardware (oscilloscope, protocol analyzer), firmware logs, and software traces to isolate root cause
Experience reading schematics and PCB layout to correlate signal integrity observations with hardware design
Excellent communication skills with the ability to document findings clearly and collaborate across multidisciplinary teams

Job Responsibility

Lead the system bring-up and validation of state-of-the-art AI scale-up switches purpose-built for high-density GPU compute racks, from initial power-on through full system validation
Perform high-speed SerDes and link bring-up, including configuring and validating Auto-Negotiation/Link Training (AN/LT), tuning TX equalization, and characterizing signal integrity across 200G/400G/800G interfaces
Execute comprehensive link qualification testing using PRBS (Pseudo-Random Binary Sequence), Snake Traffic loopback testing, and FEC (Forward Error Correction) analysis to validate BER performance at scale
Utilize LinkCAT and Broadcom SDK tools to characterize port performance, diagnose link failures, and validate PHY configurations across large port counts
Integrate and validate server management infrastructure including BMC/IPMI, Redfish API, and out-of-band management workflows for automated bring-up and health monitoring
Develop and maintain bring-up scripts and test automation (Python) to accelerate validation coverage across chassis configurations
Debug complex system-level failures spanning hardware, firmware, and software including signal integrity issues, firmware crashes, and management plane anomalies and drive issues to root cause
Collaborate with hardware, firmware, and software teams to reproduce failures, document findings, and verify fixes across platform revisions
Maintain detailed bring-up documentation, test reports, and issue tracking throughout the product development lifecycle

What we offer

AMD benefits at a glance

Fulltime

Sr. High Speed Analog Design Engineer

This job opening is for a circuit designer in a team responsible for high-precis...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong hands-on experience in DDR circuit designs in latest process technology nodes
Good technical knowledge of power-performance trade-offs in high-speed DDR and/or SerDes architectures
Direct experience in all phases of design analysis including functional, static timing and electrical sign-off
Strong understanding of the impact of variation on design performance
Masters in Electrical/Electronics Engineering, with specialization in microelectronics or something similar

Job Responsibility

Complete ownership of individual circuit blocks in a DDR PHY design in cutting edge process technology nodes
Responsible for circuit design, layout quality, electrical and timing analysis, and reliability checks
Interface with cross-functional teams like RTL, Verification and Physical Design

Senior Hardware Design Engineer

We are seeking a Senior Hardware Design Engineer to join our Product HW design t...

Location

India , Bengaluru

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electronics / Electrical Engineering or a closely related discipline
12–15 years of experience in complex hardware and system-level design, with products shipped to production
Proven ownership of high-speed board-level hardware designs
Deep understanding of Signal integrity, Power distribution networks, System level mechanical - thermal considerations
Strong experience with networking hardware platforms, such as switches, routers, or network appliances
Proficiency using Cadence PCB design tools (Concept / OrCAD, Allegro)
Strong working knowledge of common interfaces and protocols, including DDR (DDR4 / DDR5), PCIe, USB, SPI, I²C, UART, SGMII, XAUI
Experience with Ethernet PHY, MDI, and switching designs, including Gigabit, Multi‑Gig, and 10GBASE‑T
Solid understanding of SerDes technologies, including NRZ (10G, 25G), PAM4 (50G / 100G)
Experience integrating CPU subsystems (ARM, Intel x86, AMD x86)

Job Responsibility

Lead and own complex hardware designs end‑to‑end, including: Functional specifications, Component selection, Schematic capture, participate architecture decision making, Hardware bring‑up, debug, and validation
Drive high‑speed digital design decisions, addressing: Signal integrity and channel performance, Power distribution and sequencing, Timing, design margins, reliability, trade‑off decisions
Serve as the technical owner for complete boards or major subsystems within networking products
Partner closely with cross‑functional and multi‑site teams—including PCB layout, SI/PI, validation, mechanical, thermal, EMC, manufacturing, firmware, and software—to deliver production‑ready designs
Influence design feasibility, COGS, margins, and long‑term reliability through upfront analysis and hands‑on lab validation
Perform deep root‑cause analysis and empirical testing on complex hardware and system‑level issues, driving corrective and preventive actions
Contribute to and help drive design methodologies, best practices, and engineering standards
Mentor junior engineers, providing technical guidance, thorough design reviews, and coaching

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Analog Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great prod...

Location

United States , Boxborough

Salary:

169600.00 - 254400.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

PhD in Electrical Engineering or related fields or M.S. with relevant experience with extensive design experience in both optical and electrical transceiver design

Job Responsibility

Transceiver circuit/link micro-architecture definition, implementation, verification, and documentation: clock generation and distribution, data path, DSP, CDR, calibration & adaptation loops
Top-level and block-level electrical/optical link budgeting and modeling
Circuit design spec definition of transceiver building blocks (ADC, DAC, PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer, etc.)

Fulltime

Serdes Analog Mixed-Signal Design Expert

AMD Serdes Technology Group develops high-performance electrical and optical tra...

Location

United States , San Jose

Salary:

216000.00 - 324000.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

PhD in Electrical Engineering or a related field or MS with relevant industrial experience in optical and/or electrical transceiver design
experience designing 200G+ CMOS transceivers, with a deep understanding of high-speed electrical and/or optical interface requirements
demonstrated proficiency in hands-on circuit optimizations, including tuning for power, performance, and area at both block and system levels
proven track record in silicon productization—from initial design through to bring-up, validation, and successful ramp to mass production

Job Responsibility

Own performance-critical analog mixed-signal circuit blocks used in Serdes, such as high-speed data converters (DAC and ADC), clocking (reference clock, PLL, clock dividers, muxes, buffers, regulators, multi-phase clock generators, error detection and correction), and analog front-end circuits (pad matching networks, ESD, CTLE, linear amplifier)
define circuit-driven micro-architectures of Tx and Rx subsystems and drive sub-block level specs
own power, performance, area, and jitter budgets of analog design blocks
mentor sub-block owners and conduct peer reviews of design and verification results
work with pre-tapeout verification and post-silicon validation teams to bring up silicon and analyze silicon results

Fulltime

Asic Engineering Design Verification Leader

Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical tran...

Location

India , Pune

Salary:

Not provided

Duo Security

Expiration Date

Until further notice

Requirements

Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
8-12 years of functional verification experience
Strong skills in SystemVerilog, Python, C and UVM methodology
Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow
You must be a team player and be able to drive decisions quickly with consensus building
Strong analytical, problem-solving and debugging skills
Strong teamwork, communication, and organizational skills

Job Responsibility

Develop testbench components for Silicon Photonics subsystems
Develop functional coverage models, assertions, and debug complex verification issues within a UVM-based framework
Run verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions
Prior to tapeout you will run functional scenarios with CPU FW loaded and verify functionality at the CPU sub-system level
You may be involved in FPGA verification
Post Silicon you will be involved in ATE test plan and test vector generation, ATE testing and release to production

Fulltime

Senior Staff Silicon Design Engineer

The AMD SerDes team in Ireland are hiring for an SMTS level Analog Circuit Desig...

Location

Ireland , Cork

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Good analog circuit design and analysis skills
Experience with industry standard schematic entry and circuit simulation tools and methodologies
Good programming / scripting skills
Familiarity with the impact of layout effects on circuit design
Experience with circuit floorplanning
Previous experience on high speed circuit design would be a benefit
Experience in silicon debug, verification and characterization
Good interpersonal/teamwork skills
Bachelors or Masters degree in Electronic/Electrical Engineering

Job Responsibility

Analog circuit design of different circuits related to SerDes phy development to meet block level design specifications
Verification of circuit designs to ensure functional, performance and reliability targets are achieved using industry standard tools and methodologies
Regular presentation and sharing of design progress to peers
Participating in design reviews of other circuits both for identifying potential issues and also from a learning perspective
Communication with SerDes circuit team members at other sites for the purposes of sharing ideas
Feading back circuit performance information to the architecture team for the purposes of system modelling
Support of the system level verification team in the modelling of analog circuits in Verilog and in the debug of identified issues
Assist with silicon bring up and debug

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SerDes PHY Engineer

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