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The Virtual Test Engineer will own the end‑to‑end test engineering for virtual ECUs—from V‑ECU creation (AUTOSAR Classic/Adaptive) and restbus/environment modeling, to deterministic simulation, fault injection, conformance, diagnostics/flash, and scalable CI execution. You will build and operate a virtual test platform that exercises production software stacks (communication, diagnostics, safety/security, OTA readiness) with measurable coverage and release‑grade. You partner with software, systems, safety, cybersecurity, HIL, and OTA teams to ensure the virtual pipeline finds defects earlier than HIL/vehicle, at fleet scale.
Job Responsibility:
Ownership of Virtual Test topics in NAR markets
Own the relationship with network operator, contract manufacturer, platform provider and lead strategic discussions and technical negotiations
Serve as technical authority for V‑ECU testing
mentor engineers in XiL best practices, determinism, and modeling trade‑offs
Drive supplier alignment (Tier‑1/2) for virtual deliverables (V‑ECU packages, ARXML/ODX/OTX, service catalogs, security plugins)
Conduct design/test reviews, DFMEA/FMEA, and lead 8D on defects discovered in SIL with crisp reproduction artifacts
Define the V‑ECU generation strategy for AUTOSAR Classic (RTE + BSW abstraction, virtual MCAL stubs) and Adaptive (POSIX targets, ara::com SOME/IP bindings), including OS abstraction, timers, time‑warp, and determinism controls
Select and integrate V‑ECU platforms (e.g., dSPACE VEOS/SystemDesk, Vector vVIRTUALtarget/CANoe4SW Server, ETAS COSYM/ASCET, AVL VIRTUAL TESTBED, Wind River Simics, Imperas/OVPsim, QEMU/Renode‑based flows) and manage tool qualification where applicable
Establish co‑simulation topologies: MIL/Plant models (Simulink/Modelica/FMU/FMI), bus/network simulators, and virtualization of sensors/actuators with IO semantics and timing fidelity
Model and validate Automotive Ethernet stacks: SOME/IP & SOME/IP‑SD, DoIP, AVB/TSN where applicable
simulate VLAN/QoS and congestion scenarios
Exercise CAN/CAN‑FD, LIN, FlexRay via restbus simulations
verify UDS services, ISO‑TP segmentation and XCP/CCP measurement/calibration flows
Implement DoIP‑routed UDS flashing in SIL with eligibility/state checks, A/B or recovery slots, anti‑rollback, and bootloader handshake emulation (timings, NRCs)
Develop restbus models for gateways, sensors, actuators, and peer ECUs using Vector CANoe/CAPL (incl. CANoe4SW Server), Python, and co‑simulation bridges
Build service catalogs and SOME/IP service mocks, including late‑joiner/re‑announce behaviors and instance collision tests
emulate SecOC/E2E protections
Create plant models (Simulink/Modelica, FMU/FMI) for closed‑loop testing of control functions
parameterize with production DBC/ARXML/LDF
Execute fault campaigns: bus saturation, frame loss/reordering, clock drift, time sync perturbations (gPTP), power cycles/brown‑outs (virt), memory pressure, and network fuzzing (UDS/DoIP/SOME‑IP)
Apply protocol fuzzing (boofuzz, Scapy, Peach, AFL++ harnesses), mutation testing, and error seeding to validate diagnostic/communication hardening
Model electrical transients (ISO 7637‑2, load dump) effects at the software boundary and verify recovery logic within the V‑ECU
Architect headless SIL farms (Docker/K8s runners, ephemeral test environments) executing parallel suites (thousands of SIL testcases per commit/nightly)
Integrate CI/CD (Jenkins/GitLab/Azure DevOps), artifact management (SBOM: SPDX/CycloneDX), test results (JUnit/Allure), and flaky test quarantine + triage dashboards
Implement golden capture/compare pipelines (PCAP/MDF4/CSV) and scenario versioning (OpenSCENARIO/OpenDRIVE/ASAM OSI if AD/ADAS is in scope)
Requirements:
Excellent strategically thinking and communication skills
Analytical and conceptual thinking
Experience in developing strategies for R&D
Communication skills - interpersonal, presentation and written
Integration - joining people, processes or systems
Influencing and negotiation skills
Strategic/visionary minded
Resource management
Interest in designing systems
Knowledge of communication HW & SW architecture and hardware development processes
Excellent communication
proven cross‑functional leadership across hardware, software, cloud, manufacturing, compliance, and program management
Deep understanding of typical vehicle EE architectures and automotive development processes
Deep expertise in SOME/IP/SOME‑IP‑SD, DoIP, UDS/ISO‑TP, CAN/CAN‑FD/LIN, and restbus modeling
hands‑on with ODX/OTX and XCP
Proven delivery of CI‑scale virtual test grids (parallel headless execution, artifacted evidence, flake management)
Strong command of coverage engineering (MC/DC, model & code coverage), fault injection/fuzzing, and performance/timing analysis in virtual environments
Demonstrated experience with MISRA, static analysis, sanitizers, and traceability (Polarion/Codebeamer)
7+ years of hardware or software development experience for connectivity functions in a vehicle manufacturer or supplier
5+ years of working in automotive projects including communication technology, ADAS or automation
BS in Engineering
Nice to have:
MS and/or PhD in Engineering
V‑ECU generation using VEOS/SystemDesk, vVIRTUALtarget/CANoe4SW, or COSYM
co‑sim with FMU/FMI and plant models
TSN budget analysis (gPTP domains, Qav/Qbv scheduling) for AV/service traffic in SIL
Virtual UDS flashing including A/B slots and anti‑rollback
security hardening (SecOC, TLS/mTLS) validated in SIL
Experience scaling SIL in Kubernetes with observability (OpenTelemetry + ELK/Grafana) and SBOM/attestation in release flow
Exposure to ADAS scenario‑based validation (OpenSCENARIO/OSI) and cloud‑scale simulation
Knowledge of VW Group product design requirements
Programming experience with the languages C, C++, Java, Python, and script languages
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