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System Validation engineers in this group are responsible for driving validation specifications & methodology and deliver on the validation of IPs for the next generation of compute solution. You will work closely with architecture, design, verification, modelling, performance analysis, SW development, Emulation and FPGA and Board development engineers.
Job Responsibility:
Work with project team to understand, review the system requirements and deliver emulator testbench specifications
Own the development of validation platform in emulation, debug methodology, developing and implementing the test content, finding bugs, and running various validation checks for IPs (CPUs and SystemIPs), Interfaces (like CHI, PCIe etc.) in emulation environment
Guide other members of the team as needed to enable the successful completion of project activities
Requirements:
4-6 Years of Experience
Bachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering
Experience of Emulation and system level validation for IPs and sub-systems and ASIC products
Emulation build skills and knowledge for a subsystem in at least one emulation system
Execution of the design in emulation platform and knowledge of hardware and software interplay
Knowledge of Validation test content using C, C++
Expertise on hardware behavioral language (Verilog, System Verilog)
Exposure to producing validation specifications and documentation describing sophisticated designs
Ability to work under time-scale pressure and meet ambitious targets without compromising on quality
Understanding of the fundamentals of computer architecture, system IP, memory subsystem, accelerator
Practical experience of working on Processor based system designs
Nice to have:
Demonstrated understanding of CPU/ GPU subsystem in SoC environment and proven expertise in owning validation requirements & Validation Plan
Hands on Experience in validating multiple sub systems for ASICs/ SoCs in system environment ( across Emulation, FPGA and Development/Eval board), owning all phases of validation ( Test development, Execution and Debug) for owned sub systems