Senior Verification Design Engineer

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause
• work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Graphics pipeline knowledge
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Good working knowledge of SystemC and TLM with some related experience
• Scripting language experience: Perl, Ruby, Makefile, shell preferred
• Exposure to leadership or mentorship is an asset
• Bachelors or Masters degree in computer engineering/Electrical Engineering

Desirable assets with prior exposure to video codec system or other multimedia solutions