Senior Verification Design Engineer Job at AMD (BRITISH COLUMBIA)

Senior Staff Silicon Design Engineer (Design Verification)

At AMD, our mission is to build great products that accelerate next-generation c...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in ASIC/SoC design
Strong hands-on verilog development experience, familiar with scripting languages like Perl
Good experience on complicate hub,control IP design
Strong problem solving, independent thinking, teamwork and communication skills
Bachelor or Master degree in E&E or Computer Engineering. (Preferred Master Degree)

Job Responsibility

Own part of IP feature design with cooperation with other designers
As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.

What we offer

AMD benefits at a glance.

Senior Design Verification Engineer – Security IP

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great pro...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

BSc with a minimum of equivalent 5 years relevant experience
or MSc with a minimum of equivalent 3 years
or PhD in a directly related research area and a minimum of 1 year
A minimum of equivalent 10 years relevant experience if as advanced level team members
Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge of applicable state-of-art verification methodology and best practices, if as advanced level team members
Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile)
Proven skills in creating UVC and other UVM components. Experience with C-DPI and Formal Verification techniques are valuable assets
Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc.
Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates

Job Responsibility

Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure
Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure
Participate in MP subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems
Debug and solve integration issues with SoC Integration and SoC DV teams
Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members
Provide project execution leadership in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting if as advanced level team members

Fulltime

Senior Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

119800.00 - 261000.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Job Responsibility

Develop complex verification environments and test suites, including pre-silicon functional verification at the block, chip, and system levels, reference modeling, and post-silicon validation.
Collaborate with architects and design engineers to define verification plans, including strategy, test environments, and requirements for IP/Subsystem/SoC-level verification.
Create and drive comprehensive test plans and develop tests to ensure full feature coverage.
Design and implement technical solutions to address complex design and quality challenges.
Develop verification components such as scoreboards, sequences, constrained random tests, assertions, and functional coverage models.
Triage and debug failures in testbenches, simulations, and emulation environments.
Develop Makefiles and automation scripts to enable scalable and efficient verification flows.
Apply Agile methodologies, including participation in code reviews, sprint planning, and continuous integration practices.
Collaborate effectively with cross-functional teams across multiple sites and geographies.

Fulltime

Senior Design Verification Engineer – Graphics & Multimedia IP

The focus of this role is to plan, build, and execute the verification of new an...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Graphics pipeline knowledge
Developing UVM based verification frameworks and testbenches, processes and flows
Automating workflows in a distributed compute environment
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Fulltime

Senior Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Austin

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Job Responsibility

Own or lead verification of complex flows at Fabric Interconnect or at block level
Learn about the design and interact with partner teams to define verification strategies and test plans
Develop UVM-based verification environments and run and debug simulations to drive quality
Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
Innovate to improve verification efficiency through methodologies or tools
Apply industry leading generative AI solutions to verification work
Coach and mentor others in your areas of expertise
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Fulltime

Senior Design Verification Engineer

We are looking for a Senior Design Verification Engineer to join Microsoft's Sil...

Location

United States , Raleigh

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check

Job Responsibility

Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components
Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness
Develop Verification IP (VIP) components to verify home grown designs
Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments
Define and implement functional coverage and drive coverage closure
Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third-party vendor teams to ensure pre-and-post-Si testing is comprehensive
Develop scripts for verification and validation infrastructure

Fulltime

Senior ASIC Design Verification Engineer

Drive advanced verification using UVM methodology to validate complex ASIC featu...

Location

India , Bengaluru

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

15+ years of experience in ASIC Verification using SystemVerilog
Strong expertise in UVM (preferred), OVM, or VMM methodologies
Experience in constrained-random verification
Hands-on experience with ASIC debugging and problem-solving
Proficiency with simulation tools like VCS / NC-Sim
Strong scripting skills in Perl / Tcl (Python is a plus)
Exposure to networking protocols (e.g., Ethernet) is desirable
Demonstrated technical leadership and ownership mindset
B.E/B.Tech or M.E/M.Tech in Electronics or related field

Job Responsibility

Drive advanced verification using UVM methodology to validate complex ASIC features
Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM
Define, design, and execute verification plans and test suites for ASICs
Perform verification using simulation tools (VCS / NC-Sim or equivalent)
Own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off
Perform functional coverage, code coverage, and gate-level simulations (GLS)
Collaborate with RTL designers for debugging and software teams for bring-up and validation
Enhance verification infrastructure through automation using Perl, Python, or Shell scripting

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Senior Quantum Design Verification Engineer

At Microsoft, our mission is to empower every person and every organization on t...

Location

United States , Redmond

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check
proof of citizenship or permanent residency

Job Responsibility

Define pre-silicon Simulation, post-silicon Validation/Characterization plans for SoC/ intellectual property (IP)
coordinate and drive individuals, contingent staff and external vendors towards creating a high-quality design
Own and create verification environments and tests for IP level and SoC level designs
validate designs in simulation with both pre and post layout RTL/netlists
Setup Databases, flows for SoC/IP repositories
Setup Bug-Tracking systems
Drive Milestone reviews, reports/status
Create testplans for pre-silicon simulation verification including for both digital and analog components
performing Analog Mixed Signal Simulation models
Collaborate with Design for Test (DFT) team to test DFT features

Fulltime

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Senior Verification Design Engineer

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