Senior Staff Silicon Design Engineer Job at AMD (Penang)

Senior Staff Silicon Design Engineer

The AMD SerDes team in Ireland are hiring for an SMTS level Analog Circuit Desig...

Location

Ireland , Cork

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Good analog circuit design and analysis skills
Experience with industry standard schematic entry and circuit simulation tools and methodologies
Good programming / scripting skills
Familiarity with the impact of layout effects on circuit design
Experience with circuit floorplanning
Previous experience on high speed circuit design would be a benefit
Experience in silicon debug, verification and characterization
Good interpersonal/teamwork skills
Bachelors or Masters degree in Electronic/Electrical Engineering

Job Responsibility

Analog circuit design of different circuits related to SerDes phy development to meet block level design specifications
Verification of circuit designs to ensure functional, performance and reliability targets are achieved using industry standard tools and methodologies
Regular presentation and sharing of design progress to peers
Participating in design reviews of other circuits both for identifying potential issues and also from a learning perspective
Communication with SerDes circuit team members at other sites for the purposes of sharing ideas
Feading back circuit performance information to the architecture team for the purposes of system modelling
Support of the system level verification team in the modelling of analog circuits in Verilog and in the debug of identified issues
Assist with silicon bring up and debug

Senior Staff Silicon Design Engineer (Design Verification)

At AMD, our mission is to build great products that accelerate next-generation c...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in ASIC/SoC design
Strong hands-on verilog development experience, familiar with scripting languages like Perl
Good experience on complicate hub,control IP design
Strong problem solving, independent thinking, teamwork and communication skills
Bachelor or Master degree in E&E or Computer Engineering. (Preferred Master Degree)

Job Responsibility

Own part of IP feature design with cooperation with other designers
As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.

What we offer

AMD benefits at a glance.

Senior Manager Silicon Design Engineering

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Strong mentoring and coaching skills
Excellent people skills
Excellent verbal and written communication skills
Strong time management skills
Good understand of Analog Layout
Good understand of Analog Circuits
Able to review Analog Layout PDV results
Attention to detail
Good problem-solving skills

Job Responsibility

People Manager – responsible for Team Members
Career Development
Performance Management
Project Management
Able to manage multiple projects efficiently and effectively
Resource planning
Project scheduling
Project Tracking
Work closely with Engineering staff to ensure correct requirements are achieved
Project status report-out to various stakeholders

Senior Silicon Validation Engineer

HPE is seeking a Senior Silicon Validation Engineer to help validate the functio...

Location

United States , Ft. Collins

Salary:

142000.00 - 270000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

May 28, 2026

Requirements

Bachelor’s or master’s degree in electrical engineering, computer engineering, computer science or equivalent
6-10+ years of experience in VLSI Validation, verification, or design, including experience leading teams or complex projects
Senior level proficiency in object-oriented Python programming
Senior level proficiency in Linux command line, Verilog hardware description language, electronic design automation (EDA)
Senior level experience in ASIC Silicon Validation and testing is required
Senior level knowledge of industry standard networking protocols is required. (200G/400G/800G+ Ethernet, 50G/100G/200G+ SERDES (Die to Die as well as long reach))
Executive written and verbal communication skills
mastery in English
Must hold U.S. citizenship, U.S. lawful permanent resident/Green Card status

Job Responsibility

Oversees full chip-level validation, utilizing emulators and developing tests that run at the operating system level to assess both HPE Slingshot and industry standard networking protocols
Provides technical leadership for the HPE Slingshot Silicon Validation engineering team, responsible for all stages of ASIC validation for Network Interface Cards (NIC) and Switch hardware
Provides technical leadership and guidance to cross-organization projects and activities
Owns the validation strategy and risk management for major projects
Drives innovation and integration of new technologies and methodologies into Silicon Validation projects and activities
Provides input on the selection and development of future technical leaders
Mentors and develops less experienced staff members, setting an example of innovation and excellence in Silicon Validation
Represents the organization in external engagements, including partner collaborations and industry forums
Collaborates and communicates with management and internal partners regarding validation status, project progress, and issue resolution

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Member of Technical Staff, Software Co-Design AI HPC Systems

Our team’s mission is to architect, co-design, and productionize next-generation...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Bachelor's Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.
Master's Degree in Computer Science or related technical field AND 8+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR Bachelor's Degree in Computer Science or related technical field AND 12+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.
Strong background in one or more of the following areas: AI accelerator or GPU architectures
Distributed systems and large-scale AI training/inference
High-performance computing (HPC) and collective communications
ML systems, runtimes, or compilers
Performance modeling, benchmarking, and systems analysis
Hardware–software co-design for AI workloads
Proficiency in systems-level programming (e.g., C/C++, CUDA, Python) and performance-critical software development.
Proven ability to work across organizational boundaries and influence technical decisions involving multiple stakeholders.

Job Responsibility

Lead the co-design of AI systems across hardware and software boundaries, spanning accelerators, interconnects, memory systems, storage, runtimes, and distributed training/inference frameworks.
Drive architectural decisions by analyzing real workloads, identifying bottlenecks across compute, communication, and data movement, and translating findings into actionable system and hardware requirements.
Co-design and optimize parallelism strategies, execution models, and distributed algorithms to improve scalability, utilization, reliability, and cost efficiency of large-scale AI systems.
Develop and evaluate what-if performance models to project system behavior under future workloads, model architectures, and hardware generations, providing early guidance to hardware and platform roadmaps.
Partner with compiler, kernel, and runtime teams to unlock the full performance of current and next-generation accelerators, including custom kernels, scheduling strategies, and memory optimizations.
Influence and guide AI hardware design at system and silicon levels, including accelerator microarchitecture, interconnect topology, memory hierarchy, and system integration trade-offs.
Lead cross-functional efforts to prototype, validate, and productionize high-impact co-design ideas, working across infrastructure, hardware, and product teams.
Mentor senior engineers and researchers, set technical direction, and raise the overall bar for systems rigor, performance engineering, and co-design thinking across the organization.

Fulltime

New

Senior Staff Test Engineering Lead

The Technical Lead is responsible for the test solution for a next-generation AM...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor/Master in Electrical/Electronic Engineering
Strong hands-on experience supporting complex SoC products (e.g., mobile or automotive processing units)
Proven technical leadership across at least one full SoC product lifecycle (pre silicon to production)
Deep expertise in DFT and ATE test methodologies, spanning areas like ATPG Scan, MBIST, Functional, and High‑Speed IO testing across complex SoC environments
Strong experience with Advantest 93k/Teradyne test platforms
Solid understanding of CPU / GPU / SoC architectures with system level interactions
Strong programming or scripting skills (Python, C/C++, Perl, Java)
Experience with industry EDA tools (Mentor, Synopsys, Cadence)
Demonstrated ability to act as a technical decision‑maker and mentor within the test organization
Strong communication skills to engage deeply with global, cross‑functional engineering teams

Job Responsibility

Define and drive pre silicon test and characterization strategies for complex SoC products
Establish DFT and pattern requirements, and work with Design and Verification teams to ensure test readiness prior to first silicon
Lead first silicon bring up, silicon debug, and characterization execution across PVT corners
Analyze yield, performance distributions, and device failures
lead root cause analysis and drive corrective actions across global teams
Perform circuit sensitivity analysis, interpret findings, and guide deep dive investigations to resolution
Drive innovation in SoC test, debug, DFT, and test methodology, translating ideas into production ready solutions
Own test content optimization to meet product quality and cost targets
Drive yield, test time, and margin improvements from wafer sort through backend test
Partner with manufacturing and quality teams to ensure stable, scalable production

Staff Server Electrical Validation Engineer

We are seeking a highly skilled MTS Electrical Validation Engineer to join our d...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

7+ years of experience in hardware architecture, logic/circuit design, and implementation
Experience with PCIe4/5/6 or Ethernet
Familiarity with programming/scripting languages (C/C++, Python, Perl, etc.)
Working knowledge of Server OSes (Linux, Windows Server)
Familiarity with high-speed circuit testing and DFT methods
Excellent communication and leadership skills, with the ability to function independently in a fast-paced, dynamic environment
Skilled in MS Office, MS Project, Confluence, MS SharePoint, and Jira
Bachelor’s degree in Electrical/Electronic Engineering or equivalent

Job Responsibility

Lead and coordinate engineering projects, ensuring alignment with AMD management and technical guidance
Engage with internal and external stakeholders in product planning, development, and validation activities
Monitor and control project schedules and scopes, ensuring timely delivery and adherence to objectives
Facilitate team communications and reviews with senior management and customers, providing clear status updates and progress reports
Define and develop IO electrical validation requirements and test coverages to ensure compliance and success at the platform level
Develop and manage comprehensive validation strategies, plans, and schedules by integrating inputs from various engineering and business departments
Conduct hands-on measurement and characterization of Post-Si IO electrical interfaces using advanced lab equipment such as oscilloscopes, TDR, VNA, and more
Own and drive the debugging of Post-Si electrical issues, collaborating with hardware, BIOS, firmware, and OS teams to recommend effective solutions

Senior Staff Silicon Design Engineer

AMD

Location:
Malaysia , Penang

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
January 12, 2026

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Senior Staff Silicon Design Engineer

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Location:Malaysia , Penang

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Contract Type:Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:January 12, 2026

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Location:
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Job Posted:
January 12, 2026