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Senior Staff Physical Design Engineer

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AMD

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Location:
Malaysia , Penang

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of an engineering team to drive and improve AMD's abilities to deliver the MI/Navi series of GPU products to market. The Physical Design Engineering team, as part of GPU Engineering SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

Job Responsibility:

  • Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
  • Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
  • Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
  • Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
  • Clocking and top‑level mesh implementation and signoff
  • Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
  • Analyze complex cross-block and top-level signoff issues and define closure strategy
  • Define and enforce signoff criteria, methodologies, and best practices
  • Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
  • Identify risk areas early and proactively drive mitigation plans
  • Mentor senior and junior engineers
  • act as escalation point for signoff issues
  • Support post-silicon analysis and correlation (as required)

Requirements:

  • Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
  • Proven record of Physical Design signoff flow
  • Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
  • Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
  • Proven ability to work with cross-functional teams across multiple sites/time zones
  • Strong analytical, problem-solving, and communication skills
  • Familiarity with CPU and or GPU architecture
  • Proficiency in data analysis and interpretation

Additional Information:

Job Posted:
April 01, 2026

Work Type:
Hybrid work
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