This list contains only the countries for which job offers have been published in the selected language (e.g., in the French version, only job offers written in French are displayed, and in the English version, only those in English).
HPE is seeking a Senior Silicon Validation Engineer to help validate the functionality of HPE Slingshot ASIC products. HPE Slingshot is a modern high-performance interconnect for HPC and AI clusters that delivers industry leading performance, bandwidth, and low latency for HPC, AI/ML, and data analytics applications. Including multiple generations of both air and fully liquid cooled switch and NIC products, it serves as the interconnect of choice for the worlds faster supercomputers, including the top three systems on the top500.org list. This position will be an individual contributor, as well as team lead, responsible for developing object oriented Python tests for full chip-level emulation testing of a high performance computing network interconnect chips. It requires strong leadership in test development, a deep understanding of chip architecture, and the ability to recognize and adapt to generational changes in technology. A major area of responsibility is identifying the highest risk areas to ensure that silicon validation is testing gaps not covered by architecture simulations or pre-silicon verification. This position will work directly with management to facilitate resource allocation and project schedules.
Job Responsibility:
Oversees full chip-level validation, utilizing emulators and developing tests that run at the operating system level to assess both HPE Slingshot and industry standard networking protocols
Provides technical leadership for the HPE Slingshot Silicon Validation engineering team, responsible for all stages of ASIC validation for Network Interface Cards (NIC) and Switch hardware
Provides technical leadership and guidance to cross-organization projects and activities
Owns the validation strategy and risk management for major projects
Drives innovation and integration of new technologies and methodologies into Silicon Validation projects and activities
Provides input on the selection and development of future technical leaders
Mentors and develops less experienced staff members, setting an example of innovation and excellence in Silicon Validation
Represents the organization in external engagements, including partner collaborations and industry forums
Collaborates and communicates with management and internal partners regarding validation status, project progress, and issue resolution
Requirements:
Bachelor’s or master’s degree in electrical engineering, computer engineering, computer science or equivalent
6-10+ years of experience in VLSI Validation, verification, or design, including experience leading teams or complex projects
Senior level proficiency in object-oriented Python programming
Senior level proficiency in Linux command line, Verilog hardware description language, electronic design automation (EDA)
Senior level experience in ASIC Silicon Validation and testing is required
Senior level knowledge of industry standard networking protocols is required. (200G/400G/800G+ Ethernet, 50G/100G/200G+ SERDES (Die to Die as well as long reach))
Executive written and verbal communication skills
mastery in English
Must hold U.S. citizenship, U.S. lawful permanent resident/Green Card status
Nice to have:
Familiarity with high performance NIC and Switch ASICs
Senior level proficiency in Bash scripting, emulation, and/or FPGA tools