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AMD Logo AMD · IT - Software Development

Senior Silicon Design Verification Engineer

United States, San Jose 136000.00 - 204000.00 USD / Year · Job Posted March 22, 2026
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Job Description

Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.

Job Responsibility

  • Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance
  • Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level
  • Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs
  • Develop and execute comprehensive verification plans, including testbenches and test cases
  • Collaborate with design, architecture, and software teams to define and implement verification strategies
  • Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification
  • Mentor and guide junior engineers, fostering a collaborative and innovative team environment

Requirements

  • Proven track record in technical leadership of teams with 5+ engineers
  • Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS requirements
  • Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium
  • Require strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
  • Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management
  • BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science

Nice to have

  • Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs
  • Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor)
  • Experience with gate-level simulation, power-aware verification
  • Experience with silicon debug at the tester and board level
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