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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior Silicon Design Engineer to help achieve that mission.
Job Responsibility:
Own end‑to‑end design responsibilities, from architectural collaboration through silicon validation
Collaborate with SOC and IP architecture teams to define and refine IP microarchitecture
Develop microarchitecture and implement high‑quality RTL for IP blocks
Drive synthesis, static timing analysis (STA), and timing closure
Support silicon bring‑up and validation activities
Leverage high‑speed microarchitecture design experience to deliver robust, high‑performance solutions
Requirements:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Nice to have:
6+ years of hardware design experience
Experience in Digital Design including microarchitecture specification development and RTL coding
Experience in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and LINT closure
Experience in developing/optimizing high speed CMOS designs and evaluating PPA tradeoffs
Proficiency in Verilog, System Verilog, and scripting languages such as Python or Perl
Good design knowledge of the industry standard bus interfaces such as AMBA AXI protocol
Experience in basic floor planning, static timing analysis/closure and engaging with physical design teams
Experience with driving chip design quality through design and checklist reviews
Good communication and a self-motivated individual that can collaborate across teams within Microsoft
Worked in leading-edge technologies: 5 nm or newer