Senior Silicon Design Engineer

• Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration
• Work in synthesis and netlist delivery that meets timing, area and power bounding box
• Assist physical design team on the floor-planning and timing closure
• Work with Design Verification team to ensure quality for architecture definition and design implementation

• Over 5 years of digital IP/SoC development
• Good working experience in computer architecture and interconnects
• Good working experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation
• Good command of Verilog RTL design and has experience of large digital ASIC project
• Familiarity in high-speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt, UFS, Ethernet) is a plus
• Working experience in with front-end EDA tools and flows
• Working experience with Unix/Linux and scripts (tcl, perl, ruby and etc.)
• Excellent interpersonal, communication, and writing skills
• Able to provide clear and logical presentations and documentation
• Has an open mind and attitude
• Transparent
• Willing to admit and learn from mistakes
• Works well with others in a team environment
• Automating workflows in a distributed compute environment
• Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality
• Major in EE, CS or related, Master’s Degree with 3+ years or Bachelor’s with 5+ years working experiences

Familiarity in high-speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt, UFS, Ethernet)