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Senior Silicon Design Engineer (DFx)

Malaysia, Penang · Job Posted May 30, 2026
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Job Description

We are seeking a motivated DFx engineer to join our SBIO design team. In this role, you will contribute to the next generation of AMD's silicon innovation while developing your expertise in DFx methodologies and advanced design practices. You will be part of a forward‑thinking engineering organization that values learning, encourages fresh ideas, and empowers emerging talent to grow into impactful contributors who help shape the future of semiconductor technology.

Job Responsibility

  • Implement and verify DFT features such as SCAN, MBIST, and BSCAN
  • Perform Spyglass DFT bring-up, debug and coverage improvement
  • Perform scan insertion and ATPG (Traditional, Cell Aware, SSN) pattern generation
  • Verify ATPG patterns using gate level simulation
  • Analyze and improve ATPG and DFT DV test coverage
  • Develop and debug DFT verification tests
  • Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure
  • Provide post silicon support to ensure successful bring up

Requirements

  • Bachelors or Masters degree in computer engineering/Electrical Engineering
  • Experience in scan stitching and strong knowledge of scan stitching concepts
  • Exposure to MBIST/BISR implementation and the Synopsys SMS MBIST insertion flow
  • Excellent hands on ATPG experience and familiarity with ATPG related file requirements
  • Knowledge or experience with Tessent SSN (Siemens) is a plus
  • Knowledge of Spyglass DFT
  • Good in C++ and object-oriented programming concepts
  • Familiarity with automation scripts such as Perl or Python is a plus
  • Understanding of JTAG and IJTAG fundamentals
  • Exposure to AI related work is a plus
  • Experience with post silicon bring up is a plus
  • Exposure to static timing analysis and timing closure is a plus

Nice to have

  • Knowledge or experience with Tessent SSN (Siemens)
  • Familiarity with automation scripts such as Perl or Python
  • Exposure to AI related work
  • Experience with post silicon bring up
  • Exposure to static timing analysis and timing closure
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