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At Cisco, Bangalore, the Common Hardware Group (CHG) architects, designs, builds, and delivers world-class Access, Edge, Aggregation, and Core routers that cater to the growing bandwidth demands of leading service providers and large enterprises.
Job Responsibility:
Be responsible for delivering system-level signal and power integrity solutions for large sophisticated high-speed systems, boards & packages
Develop SI rules, review design implementation, build test plans, and document characterization & measurement reports
Improve & optimize design margins through interconnect, timing and crosstalk analysis, 3D EM & channel simulations for high-speed designs
Design & characterize test structures & channel models to correlate simulations with measurements for Serdes and interconnects
Collaborate with multi-functional teams - HW, PCB Layout, SW, MFG, ASIC
Be responsible for electrical characterization and verification of Transmitter/Receiver SERDES settings to meet the industry standards and internal Cisco requirements
Requirements:
Bachelor's or Master’s Degree in Electrical Engineering
6+ yrs of demonstrated ability in hardware design with emphasis on Signal and Power Integrity
Hands on exposure to lab measurements including real-time scope, sampling scope, Spectrum analyzer, VNA & TDR
Good understanding of EM and transmission line concepts, timing, jitter, crosstalk, noise, channel modeling, channel equalization techniques, power delivery & decoupling
Experience with 56G PAM4, 25G & 10G NRZ Serdes technologies, and DDR - simulation, bring up, debug, measurements, and optimization
Thorough knowledge of PCB stack-up design - standard processes, performance vis-à-vis PCB materials, surface finishes, vendor capabilities, and manufacturing trade-offs
Proficiency with simulation and analysis tools like ADS, HFSS, HSPICE, Cadence Allegro, PowerSI, MATLAB, and Hyperlynx
Excellent oral and written communication skills and capability to present concepts, analysis, and updates to larger teams and forums