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Senior RTL Design Lead

India, Bangalore · Job Posted March 25, 2026
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Job Description

We are seeking a seasoned Principal design engineer with expertise or significant interest in fabric design for complex SOC. You have had significant success driving architecture, product roadmaps and product requirements. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives.

Job Responsibility

  • Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets
  • Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design
  • Micro-architecture and RTL coding in Verilog/SystemVerilog
  • Lead design on one or more domains
  • Work with architects and design leads to identify and assess complex technical issues
  • Work closely with verification teams to ensure quality component development
  • Work closely with Physical design to ensure quality PPA targets
  • Post silicon support to ensure successful bring up
  • Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
  • Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power
  • Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
  • Knowledge sharing and other contributions to Platform & System Architecture
  • As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests
  • Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
  • Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

Requirements

  • Excellent foundation in fabric/transport architecture and coherency
  • Experience in memory design/cache design
  • Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
  • Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
  • Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
  • Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
  • Excellent communication, management, and presentation skills
  • Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
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