Senior RTL Design Engineer Job at Duo Security (Yerevan)

Senior RTL Design Engineer

This is a hybrid role with four days per week at Cisco’s Yerevan office. Join th...

Location

Armenia , Yerevan

Salary:

Not provided

Duo Security

Expiration Date

Until further notice

Requirements

6+ years of industry experience in ASIC digital design
Proficient in Verilog/System Verilog coding
Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification)
Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories
Ability to write scripts using Python, Tcl, Make

Job Responsibility

Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification
Sub-system/SoC integration and verification
Review/enhancement of RTL codes
Improve flows and methodologies to streamline IP/SoC development and integration
Work closely with the verification team for complex debugs to resolve verification failures
Close interaction with the physical design team to reach better physical design QoR

Fulltime

Senior RTL Design Engineer

Join the Silicon One Team at Cisco in Armenia, a group at the forefront of devel...

Location

Armenia , Yerevan

Salary:

Not provided

Cisco

Expiration Date

Until further notice

Requirements

6+ years of industry experience in ASIC digital design
Proficient in Verilog/System Verilog coding
Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification)
Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories
Ability to write scripts using Python, Tcl, Make

Job Responsibility

Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification
Sub-system/SoC integration and verification
Review/enhancement of RTL codes
Improve flows and methodologies to streamline IP/SoC development and integration
Work closely with the verification team for complex debugs to resolve verification failures
Close interaction with the physical design team to reach better physical design QoR

Fulltime

Senior RTL Design Engineer

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platf...

Location

Armenia , Yerevan

Salary:

Not provided

Cisco

Expiration Date

Until further notice

Requirements

5+ years of industry experience in ASIC digital design
Proficient in Verilog/System Verilog coding
Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification)
Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories
Ability to write scripts using Python, Tcl, Make
Good communications skills, self-motivated and well-organized

Job Responsibility

You will be a key member of the Silicon One development organization, collaborating closely with Front-end RTL and backend physical design teams to gain a deep understanding of chip architecture
Your primary focus will be to drive high-quality Design for Test (DFT) verification, ensuring robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation
Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification
Sub-system/SoC integration and verification
Review/enhancement of RTL codes
Improve flows and methodologies to streamline IP/SoC development and integration
Work closely with the verification team for complex debugs to resolve verification failures
Close interaction with physical design team to reach better physical design QoR

Fulltime

Senior RTL Design Engineer

As a member of the Server SoC Group, you will help bring to life cutting-edge de...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Understanding SoC Design aspects that includes Clocking, IO, Latency, Reset, Fuse map, SoC Topology Networks
12+ years of experience in SoC Integration activities and definition of micro architecture
Experience with Verilog, Perl/Shell scripting, and all RTL quality checks
Triaging and debugging issues reported by Verification teams
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Work with SoC Architects, IP Design Teams and define micro architecture that includes clocking, reset, IO, Fuse
Implement SoC Design features/blocks, own connectivity across IP's
Work with Physical Design Team and deliver/triage all collaterals required for PD and implement SoC topology networks based on Full Chip floorplan and other Physical Design requirements
Own and drive RTL Quality checks/Audit that includes Lint/CDC/VCLP/Connectivity

Fulltime

Senior RTL Design Engineer – Accelerator IP

Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Enginee...

Location

United States , Austin

Salary:

117000.00 - 175000.00 USD / Year

Ericsson

Expiration Date

Until further notice

Requirements

Several years of RTL design in complex ASIC/IP environments
Expert SystemVerilog/Verilog skills
End-to-end ASIC flow mastery: coding, linting, CDC, synthesis, timing closure
Proven ability to distill DSP, FEC, or other L1 processing algorithms into high-performance hardware
Equally comfortable deep-diving into code and shaping high-level architecture strategies
A collaborative powerhouse who thrives in an intense, creative, close-knit environment

Job Responsibility

Transform high-level architectural vision into blazing-fast, reliable RTL (SystemVerilog/Verilog)
Take complete ownership of major IP blocks—specification, microarchitecture, RTL creation, synthesis, and delivery
Act as the go-to technical lead for verification, backend/PD, and architecture teams
Drive optimizations to balance power, area, and throughput without compromising innovation
Lead critical design decisions that steer the next generation of telecom hardware

What we offer

Choice of three medical plan options
Dental plan option
Company credits for medical and dental premiums
Ericsson US 401(k) Plan with automatic 3% company contribution and matching
Company credits for basic life insurance, basic accidental death and dismemberment coverage, short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
Minimum of 15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time

Fulltime

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Direc...

Location

United States , Irvine

Salary:

125000.00 - 195000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 6 years of demonstrated experience in FPGA design
4 years of FPGA design experience with a Master of Science degree
2 years of FPGA design experience with a PhD
Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
Proven expertise working with multiple clock-domain, high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Digital design architecting for wireless communication projects
Fixed point design of signal processing blocks while working with systems engineers
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering teams

Fulltime

Senior RTL to Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Redmond

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check

Job Responsibility

Be a key link between front-end design and back-end teams
Lead in the enablement of quality RTL and collateral file drops to PD
Implement feedback and mitigations in the design constraints and toolchain to ensure best-case PPA
Coordinate with RTL, DFT, CAD and physical design teams
Participate in flow development, design automation, and correlation exercises to back-end flows
Work with limited direction and have attention to detail
Provide crisp status of progress, issues, and risks on the program to the management team

Fulltime

Senior Staff Silicon Design Engineer (Design Verification)

At AMD, our mission is to build great products that accelerate next-generation c...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in ASIC/SoC design
Strong hands-on verilog development experience, familiar with scripting languages like Perl
Good experience on complicate hub,control IP design
Strong problem solving, independent thinking, teamwork and communication skills
Bachelor or Master degree in E&E or Computer Engineering. (Preferred Master Degree)

Job Responsibility

Own part of IP feature design with cooperation with other designers
As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.

What we offer

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Senior RTL Design Engineer

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