Senior RTL Design Engineer Job at AMD (Hyderabad)

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Direc...

Location

United States , Irvine

Salary:

125000.00 - 195000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 6 years of demonstrated experience in FPGA design
4 years of FPGA design experience with a Master of Science degree
2 years of FPGA design experience with a PhD
Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
Proven expertise working with multiple clock-domain, high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Digital design architecting for wireless communication projects
Fixed point design of signal processing blocks while working with systems engineers
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering teams

Fulltime

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical i...

Location

United States , Batavia, Illinois

Salary:

Not provided

NHanced Semiconductors

Expiration Date

Until further notice

Requirements

US Citizenship
5+ years of experience in physical design, specifically in ASIC, SoC, or advanced packaging (2.5D, 3DIC) technologies
Hands-on experience with Git-based version control systems for managing design revisions
Experience with timing closure and signal integrity
Proficiency in Cadence tools for physical design, timing analysis, and signoff
Strong understanding of RTL-to-GDSII flows, including floorplanning, power planning, place-and-route, and timing closure
Working knowledge of parasitic extraction (PEX), power integrity (PI), and thermal analysis in multi-die environments
Ability to work independently with minimal supervision and drive tasks to completion
Excellent verbal and written communication skills for collaboration across engineering teams
Strong debugging skills and ability to analyze tool reports, logs, and simulation results

Job Responsibility

Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
Ensure design compliance with timing, power, and area (PPA) requirements, as well as DFM, DRC, and LVS constraints
Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff
Develop and execute timing closure strategies, working with STA engineers to meet performance goals
Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments
Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration
Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration
Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions
Utilize Git-based version control workflows for design database management and collaborative development
Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs

Senior RTL to Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Redmond

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check

Job Responsibility

Be a key link between front-end design and back-end teams
Lead in the enablement of quality RTL and collateral file drops to PD
Implement feedback and mitigations in the design constraints and toolchain to ensure best-case PPA
Coordinate with RTL, DFT, CAD and physical design teams
Participate in flow development, design automation, and correlation exercises to back-end flows
Work with limited direction and have attention to detail
Provide crisp status of progress, issues, and risks on the program to the management team

Fulltime

Senior Security Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

Portugal , Moreira, Porto

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Knowledge about RTL design of hardware IP components
5+ years’ experience in RTL design or verification of hardware IP components
Knowledge of ASIC verification using System Verilog, UVM, or Verilog
Ability to create detailed specifications for test environments
MSc or PhD in Electrical Engineering or Computer Science
Strong understanding of IC Design flows and exceptional problem-solving and debugging skills
A strong communicator with excellent written and verbal skills
A team player who thrives in a collaborative international environment
An innovative thinker who is passionate about technology and continuous improvement
Detail-oriented and committed to delivering high-quality work

Job Responsibility

Designing and implementing RTL in Verilog and/or System Verilog for Security Applications
Creating and designing test environments for digital hardware Security IP cores and subsystems using System Verilog and UVM
Conducting hardware verification of IP cores and subsystems utilizing modern verification techniques such as UVM or formal verification
Collaborating with hardware and software security experts to perform functional and performance analysis of embedded hardware/software IP solutions
Working within an international team setup, contributing to global projects
Ensuring adherence to high-quality standards and best practices in digital design and verification processes

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Senior SoC Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Required to provide either proof of country of citizenship or proof of US residency or other protected status for assessment of eligibility to access export-controlled information
8+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure
6+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs
4+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug

Job Responsibility

Part of the SOC design team driving many facets of high performance, high bandwidth designs
Working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, System on Chip (SOC) integration including clocking and resets, Synthesis and static checks such as Lint and Clock/Reset domain crossings
Interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec

Fulltime

Senior FPGA Design Engineer

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

Design and implement RTL using Verilog and SystemVerilog for complex FPGA systems
Translate high-level requirements into detailed architecture and design specifications
Execute full FPGA design flow including synthesis, place and route, and timing closure
Develop and optimize designs for high-speed, high-performance applications
Work across multiple clock domains including asynchronous CDC handling
Collaborate with verification teams to ensure functional correctness and coverage
Debug and resolve design, timing, and hardware issues at block and system levels
Support hardware bring-up, lab validation, and system integration activities
Utilize FPGA toolchains such as Xilinx Vivado or Intel Quartus
Implement and integrate high-speed interfaces such as PCIe, Ethernet, DDR, SPI, and I2C

Job Responsibility

Design and implement RTL using Verilog and SystemVerilog for complex FPGA systems
Translate high-level requirements into detailed architecture and design specifications
Execute full FPGA design flow including synthesis, place and route, and timing closure
Develop and optimize designs for high-speed, high-performance applications
Work across multiple clock domains including asynchronous CDC handling
Collaborate with verification teams to ensure functional correctness and coverage
Debug and resolve design, timing, and hardware issues at block and system levels
Support hardware bring-up, lab validation, and system integration activities
Utilize FPGA toolchains such as Xilinx Vivado or Intel Quartus
Implement and integrate high-speed interfaces such as PCIe, Ethernet, DDR, SPI, and I2C

Fulltime

Pmts Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great pro...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

14–18+ years of semiconductor design experience
Strong hands‑on RTL design and microarchitecture ownership, with designs that progressed through PD and tapeout
Direct experience working within or closely alongside Physical Design teams
Deep understanding of SDC intent, timing, clocking, partitioning, and physical closure trade‑offs
Proven ability to resolve PD issues through architectural and RTL‑level solutions, not late physical workarounds
Experience driving or contributing to shift‑left initiatives or early physical feasibility analysis
Comfort operating as a senior technical authority, making cross‑domain engineering decisions
Exposure to AI‑assisted or highly automated design flows is a strong plus
Own creation and maintenance of physical‑aware RTL to enable PNR hierarchy, including partitioning, feedthroughs, repeaters, and physical intent insertion
Partner with SOC Design to translate logical IP integration into physical‑aware RTL and with IP design team creation digital‑on‑top RTL wrappers for analog IPs

Job Responsibility

Own Physical Design shift‑left strategy, ensuring PD risks are identified at RTL, SDC, and paper‑floorplan stages
Act as chief engineering authority for AI‑assisted and automated PD execution, defining where AI can act autonomously and where human judgment is required
Bridge RTL, microarchitecture, and PD, translating early PD findings into architectural and RTL‑level corrective actions
Define and enforce PD readiness and quality bars across synthesis, PnR, STA, and physical closure
Lead predictive closure and risk management, using early indicators to forecast timing, ECO churn, and execution complexity
Govern signoff readiness, ensuring AI‑augmented flows never compromise correctness or confidence
Codify execution playbooks and best practices to reduce variability and scale high‑quality PD execution across teams
Serve as a trusted technical peer to RTL architects, PD leads, and AI/methodology owners

Fulltime

Senior RTL Design Engineer – Accelerator IP

Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Enginee...

Location

United States , Austin

Salary:

117000.00 - 175000.00 USD / Year

Ericsson

Expiration Date

Until further notice

Requirements

Several years of RTL design in complex ASIC/IP environments
Expert SystemVerilog/Verilog skills
End-to-end ASIC flow mastery: coding, linting, CDC, synthesis, timing closure
Proven ability to distill DSP, FEC, or other L1 processing algorithms into high-performance hardware
Equally comfortable deep-diving into code and shaping high-level architecture strategies
A collaborative powerhouse who thrives in an intense, creative, close-knit environment

Job Responsibility

Transform high-level architectural vision into blazing-fast, reliable RTL (SystemVerilog/Verilog)
Take complete ownership of major IP blocks—specification, microarchitecture, RTL creation, synthesis, and delivery
Act as the go-to technical lead for verification, backend/PD, and architecture teams
Drive optimizations to balance power, area, and throughput without compromising innovation
Lead critical design decisions that steer the next generation of telecom hardware

What we offer

Choice of three medical plan options
Dental plan option
Company credits for medical and dental premiums
Ericsson US 401(k) Plan with automatic 3% company contribution and matching
Company credits for basic life insurance, basic accidental death and dismemberment coverage, short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
Minimum of 15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time

Fulltime

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Senior RTL Design Engineer

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