Senior RTL Design Engineer – Accelerator IP

Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Engineer and own the microarchitecture of next‑generation L1 accelerators from blank page to silicon. If you thrive on translating complex DSP/FEC algorithms into high-performance SystemVerilog, making tough power/area/throughput trade-offs, and delivering end-to-end IP in a lean, high-impact team—this is the role where your work will be seen and felt across world-class telecom products Step into a role where you’re not just another engineer—you’re a core architect of breakthrough telecom hardware. At Ericsson’s Accelerator IP team, we’re designing custom microarchitecture accelerators for EMCA L1 processing that push the boundaries of performance and innovation.