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Microsoft's Quantum team is building the first scalable, fault-tolerant quantum computer, advancing everything from quantum hardware and error correction to Azure integration. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. As quantum computing enters a pivotal phase of accelerated growth, this position offers a unique opportunity to contribute meaningfully to a transformative technology, such as the Application Specific Integrated Circuits (ASICs) and analog circuitry developed by this team. As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum analog infrastructure, driving Analog Layout designs and coordinating employees, contingent staff, and external vendors to deliver high-quality designs. Microsoft’s mission is to empower every person and every organization on the planet to achieve more.
Job Responsibility
Deliver Schematic-to-Graphic Database System (GDS) layouts for cutting-edge, high-performance, high-speed, low-power IP designs, including interconnectivity solutions and foundational Analog circuit blocks
Execute these layouts across multiple process nodes, including deep Fin Field-Effect Transistor (FinFET), following industry best practices
Develop plans for Analog Mask Layout execution and follow processes and methodologies to deliver IP blocks
Coordinate tasks with junior layout team members as needed
Using Cadence Virtuoso (or other equivalent) design tools and flows
perform layout implementation of analog-intensive IPs and help establish flows, methodologies, and processes for execution alongside peers
Support the on-boarding and off-boarding of contingent layout staff and vendor partners as needed
help direct their day-to-day execution to ensure quality and schedule are met
Work with other members of the team to deliver IPs, including project planning, schedule tracking, and report generation
Follow, augment, or put in place processes and methodologies for high-quality execution alongside peers
Other: Embody our culture and values.
Requirements
Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role, including the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status for assessment of eligibility to access the export-controlled information
Ability to leverage AI tools to drive innovation and efficiency
Ability to work in an AI-first environment using modern AI tools to accelerate discovery through hardware development.
Nice to have
10+ years of experience in Analog Mask Layout execution and IP delivery, including delivery of medium-to-large complexity analog blocks into mass production
5+ years of lead experience covering day-to-day task coordination and overall delivery responsibilities across a layout team
Proficient use of Electronic Design Automation (EDA) tools from Cadence, Mentor, and Synopsys, including advanced Schematic-Driven Layout (SDL)
Hands-on layout experience with high-performance analog blocks such as Voltage-Controlled Oscillators (VCOs), charge pumps, interpolators, bandgap references, Operational Transconductance Amplifiers (OTAs), Phase-Locked Loops (PLLs), Analog-to-Digital and Digital-to-Analog Converters (ADCs/DACs), Low-Dropout Regulators (LDOs), Serializer/Deserializers (SerDes), and other foundational analog blocks
In-depth knowledge of analog design and layout guidelines for high-performance, high-speed, and/or low-power designs, including floor-planning, block-level routing, and large macro-level assemblies
Knowledge of industry-standard analog layout techniques such as common-centroid layout, matching, symmetrical layouts, signal shielding, use of dummy devices, and thermal-aware layouts with consideration for Electromigration/IR-drop (EM/IR) and other analog-specific guidelines
Demonstrated ability to coordinate execution with external vendors and contingent staff, including scoping deliverables, tracking progress, and accepting completed work
Ability to learn cryogenic Process Design Kits (PDKs) and apply analog layout techniques to designs that operate at cryogenic temperatures.
What we offer
Certain roles may be eligible for benefits and other compensation
Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay