Senior Physical Design Engineer Job at Microsoft Corporation (Gelugor)

Job Description

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, Silicon Manufacturing and Package Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Physical Design Engineer to join the team. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Job Responsibility

Own and drive floorplanning and design planning for optimizing Mixed-Signal IPs with Analog and Digital components
Own and drive execution from synthesis to place and route of IPs, all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
Define Analog / Digital interfaces to facilitate design convergence and optimize power delivery for optimal performance (topmetal & bump planning)
Have close collaboration with RTL team to help drive and resolve design issues related to toplevel and block closure.
Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
Make good independent technical trade-offs between power, area, and timing.
Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset.

Requirements

BS/MS in Electrical or Computer Engineering
8+ years of experience
Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Innovus etc.
Strong understanding of constraints generation, STA, timing optimization, and timing closure.
Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

Nice to have

Experience in power rollup methodology and hand-on power rollup activities at block and fullchip level.
Tape-out experience in the latest foundry process nodes.
Excellent project management skills and ability to juggle multiple projects at once.
Strong understanding of constraints generation, STA, timing optimization, and timing closure.
In-depth understanding of design tradeoffs for power, performance, and area.
Solid hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Innovus etc.
Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise.
Strong problem-solving and data analysis skills
Strong automation skills using scripting languages such as Perl, TCL, Python.

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Senior Physical Design Engineer

Job Description

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