Senior Physical Design Engineer Job at AMD (Penang)

Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

Malaysia , Gelugor

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

BS/MS in Electrical or Computer Engineering
8+ years of experience
Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Innovus etc.
Strong understanding of constraints generation, STA, timing optimization, and timing closure.
Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

Job Responsibility

Own and drive floorplanning and design planning for optimizing Mixed-Signal IPs with Analog and Digital components
Own and drive execution from synthesis to place and route of IPs, all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
Define Analog / Digital interfaces to facilitate design convergence and optimize power delivery for optimal performance (topmetal & bump planning)
Have close collaboration with RTL team to help drive and resolve design issues related to toplevel and block closure.
Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
Make good independent technical trade-offs between power, area, and timing.
Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset.

Fulltime

Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
This role will require access to information that is controlled for export under export control regulations.
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status.
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport.

Job Responsibility

Experience and knowledge on Synthesis, RTL / DFT feedback , Timing Constraints.
Responsible for RTL to GDS implementation in Physical Design domain for production flagship projects.
Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners.
Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
Demonstrate technical expertise across various domains of Physical Design & Timing Signoff.
Lead and manage floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA).
Drive end-to-end execution from synthesis through place-and-route for block execution, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes.
Foster collaboration across teams to deliver solutions, aligned with a One Microsoft mindset.
Clear communications on project status & planning.

Fulltime

Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Bachelor's or master’s in electrical or computer engineering or related field with 8+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Physical Design tasks at block, subsystem, sub-chip, and/or full-chip level
Tasks will include Floorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM
May also be involved in Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection
Work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team

Fulltime

Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter

Job Responsibility

Responsible for Hierarchical Design Planning and partitioning strategies
Responsible for RTL to GDS implementation in Physical Design domain
Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential
Help influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach
Execute floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA)
Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification
Develop guidelines, checklists, and best practices for top-level physical design
Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes
Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset
Demonstrate technical expertise across various domains of Physical Design & Timing Signoff

Fulltime

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical i...

Location

United States , Batavia, Illinois

Salary:

Not provided

NHanced Semiconductors

Expiration Date

Until further notice

Requirements

US Citizenship
5+ years of experience in physical design, specifically in ASIC, SoC, or advanced packaging (2.5D, 3DIC) technologies
Hands-on experience with Git-based version control systems for managing design revisions
Experience with timing closure and signal integrity
Proficiency in Cadence tools for physical design, timing analysis, and signoff
Strong understanding of RTL-to-GDSII flows, including floorplanning, power planning, place-and-route, and timing closure
Working knowledge of parasitic extraction (PEX), power integrity (PI), and thermal analysis in multi-die environments
Ability to work independently with minimal supervision and drive tasks to completion
Excellent verbal and written communication skills for collaboration across engineering teams
Strong debugging skills and ability to analyze tool reports, logs, and simulation results

Job Responsibility

Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
Ensure design compliance with timing, power, and area (PPA) requirements, as well as DFM, DRC, and LVS constraints
Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff
Develop and execute timing closure strategies, working with STA engineers to meet performance goals
Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments
Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration
Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration
Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions
Utilize Git-based version control workflows for design database management and collaborative development
Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs

Asic / Physical Design Engineer (Int, Senior and Principal)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

8+ years in ASIC Physical Design / Backend Implementation (PnR)
End-to-end experience from netlist to GDSII (full physical design flow)
Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
Proven timing closure expertise (setup/hold, ECO implementation)
Deep experience with Synopsys and/or Cadence tool suites
Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
Strong Static Timing Analysis (STA) and timing report analysis
Experience with clock tree synthesis (CTS) and clock optimization
Solid understanding of DRC/LVS and physical verification flows
IR drop / power integrity analysis and optimization experience

Fulltime

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Senior SoC/ASIC Physical Design Engineer

About the Job: We are seeking a highly skilled Senior SoC/ASIC Physical Design E...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (Master’s preferred)
10+ years of experience in ASIC/SoC physical design and flow development
Expertise in RTL-to-GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools, understanding tool capabilities and underlying algorithms
Proficient in physical design methodologies: synthesis, place & route, STA, formal verification, CDC, and power analysis
Knowledge of FinFET and deep sub-micron CMOS technologies, including power dissipation, leakage, and dynamic behavior
Familiarity with DFT, Scan, MBIST, and LBIST methodologies and their impact on physical design
Proficient in scripting languages (Python, Tcl, Perl, bash/csh) and automation using Makefiles
Skilled in extraction and analysis of design parameters, QOR metrics, and implementing voltage scaling (SVS, DVFS) and SRAM split rail architectures
Proven ability to work collaboratively in dynamic environments, lead design closure activities, and drive execution with a proactive, solution-oriented mindset

Job Responsibility

Develop and Implement PD Flow: Establish a modern physical design (PD) flow utilizing the latest EDA tool fusion and machine learning (ML) techniques to maximize PPA efficiency, optimize resource allocation, and achieve industry-leading time-to-closure and tapeout
End-to-End Physical Design Execution: Perform partition synthesis and physical implementation, including synthesis, floorplanning, power/ground grid generation, place & route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks
Methodology and Automation: Create and refine physical design methodologies and automation scripts to streamline implementation and signoff processes
Cross-Functional Collaboration: Work closely with RTL, DFT, and ASIC design teams to define architectural feasibility, establish timing, power, and area targets, and explore design trade-offs
Drive Design Closure: Utilize an objective, metrics-driven approach to resolve design, timing, and flow issues and ensure predictability in achieving project milestones
Signoff Ownership: Lead signoff closure activities, including static timing analysis (STA), noise analysis, logic equivalency, physical verification, and power integrity (EM/IR)

What we offer

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