Senior Manager Silicon Design Engineering Job at AMD (Penang)

Senior IoT/Firmware Engineer

We are looking for a Senior IoT/Firmware Engineer to join our client’s team. Our...

Location

Portugal , Leiria

Salary:

Not provided

Precise

Expiration Date

Until further notice

Requirements

Bachelor / Master’s degree in Computer Science Engineering or equivalent
Over 5 years of experience developing embedded systems
Familiar with microcontrollers and/or microprocessors
Proficiency in firmware programming languages such as C or C++
Experience working with Real Time Operating Systems (RTOS)
Experience with communication protocols: MQTT, Ethernet, I2C, RS232, RS485, SPI
Experience with ARM, ESP32, and/or Silicon Labs technologies highly valued
Experience with Cybersecurity implementation for embedded systems (encryption, certificate management)
Executing code reviews and documentation
Experience with project budgeting, cost estimating and scheduling

Job Responsibility

Developing high-performing and reliable firmware for embedded systems using microcontrollers, sensors and analogue/digital interface circuits
Working with hardware engineering in developing future products, including recommendations on new technologies and design best practices
Coordinating the definition of architectural concepts
Collaborating with multidisciplinary teams
Ensuring compliance with regulations
Keeping up with technological advancements
Engaging in lifelong learning, attending conferences, workshops, and training sessions to enhance knowledge and skills
Fostering a culture of continuous improvement in the organization
Managing projects
Mentoring other members

Fulltime

Senior Manager Silicon Design Engineer

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

12-15 years full-time experience in IP hardware design
Proven experience managing and leading engineering teams
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
Clock domain crossing (CDC) tools
Detailed understanding of SoC design flows
Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
Outstanding interaction skills while communicating both written and verbally
Ability to work with multi-level functional teams across various geographies
Outstanding problem-solving and analytical skills

Job Responsibility

Lead a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies
Help bring to life cutting-edge designs, working closely with architecture, physical design, and product engineers to achieve first pass silicon success
Design of IP and subsystems with integration of AMD and other 3rd party IPs
Work collaboratively with other members of the IP team to support design verification, implementation, synthesis, constraints, static timing analysis, and delivery to SOC
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up

Technical Project Manager - Optical Test Systems

We are seeking an experienced and dynamic Technical Project Manager with a stron...

Location

United States , North Reading

Salary:

140500.00 - 224800.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Optical Engineering, Physics, Electrical Engineering or related discipline
master’s degree is preferred
certifications in optical engineering are a plus
5+ years experience in optical systems design and project management
Certification in Project Management (e.g., PMP, PRINCE2) is preferred
Proven track record of successfully managing complex projects from inception to completion
Strong understanding of optical principles, systems, and technologies
Proficiency in project management tools and software (e.g., Primavera, Microsoft Project)
Ability to work effectively in a fast-paced, dynamic environment
Strong problem-solving and analytical skills

Job Responsibility

Lead and manage projects involving the design, development, and deployment of optical test systems
Collaborate with cross-functional teams, including marketing, systems engineering, design engineering, and operations to ensure project milestones are met
Develop project plans, timelines, and budgets, and monitor progress against these metrics
Identify and mitigate risks and challenges throughout the project lifecycle
Communicate project status, updates, and issues to stakeholders, senior management, and customers
Provide technical guidance and support to team members and clients
Manage project documentation, including specifications, design documents, test plans, and reports
Foster a culture of continuous improvement and innovation within the project team

What we offer

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs

Senior SoC HW (Functional) Validation Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Applied understanding of Computer Architecture and CPU/SoC validation principles, including: Understanding of SoC subsystem, SoC system level, and platform level functionality and writing scripts/software with industry standard languages like Python or C/C++
At least 5+ years of experience
Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams
Verification, logic development, validation, or validation tools experience as part of a CPU, SoC and/or IP development team
Leadership skills
Demonstrated validation expertise in one or more of the following: Functional: Core, cache Coherency/mesh/fabric, PCIe/ IO, Memory Controller, Power Management
Power and Performance
Automation, Content Creation, or Tools/Scripts Development

Job Responsibility

Own post-silicon validation of one of the following areas – functional validation of cache Coherency/mesh/fabric
Define, guide, and contribute to the implementation of silicon debug tools and capabilities
Become an expert on the overall architecture, implementation of complex features/flows/protocols, and their interactions with other parts of the SoC, with the platform, and with software
Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise
Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements
Apply your knowledge of validation principles and techniques and your judgement to write test plans and implement them by developing test content, scripts, tools and other validation collateral
Execute content in post-silicon, triage and debug failures
Apply your growth mindset to learn and adapt in a complex and dynamic environment
Engage with partners to drive continuous improvement to the design, to validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably
Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers

Fulltime

Senior Manager - ASIC Development Engineering

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.Tech / M.Tech / Phd in Electronics, Computer science or Electrical Engineering
Minimum 14+ years of experience in DFT
Strong understanding of DFT Architecture
Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology
Proven track record of driving DFT architecture in complex ASIC designs
Work independently on multiple complex DFT problems across different projects
Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs)
Proficiency in SCAN, MBIST implementation
Solid understanding of JTAG & BSDL standards
Good understanding on Test clocking requirements, Test mode timing closure

Job Responsibility

DFT Architecture definitions for SoC development
Leading complex activities and providing solutions for complex DFT problems
Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs
Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies
Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs
Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology

Fulltime

Senior Manager - ASIC Development Engineering

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.Tech / M.Tech / Phd in Electronics, Computer science or Electrical Engineering
Minimum 14+ years of experience in DFT
Strong understanding of DFT Architecture
Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology
Proven track record of driving DFT architecture in complex ASIC designs
Work independently on multiple complex DFT problems across different projects
Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs)
Proficiency in SCAN, MBIST implementation
Solid understanding of JTAG & BSDL standards
Good understanding on Test clocking requirements, Test mode timing closure

Job Responsibility

DFT Architecture definitions for SoC development
Leading complex activities and providing solutions for complex DFT problems
Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs
Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies
Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs
Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology

Fulltime

Senior Manager - ASIC Development Engineering (DFT,MBIST,SCAN)

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.Tech / M.Tech / Phd in Electronics, Computer science or Electrical Engineering
Minimum 14+ years of experience in DFT
Strong understanding of DFT Architecture
Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology
Proven track record of driving DFT architecture in complex ASIC designs
Work independently on multiple complex DFT problems across different projects
Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs)
Proficiency in SCAN, MBIST implementation
Solid understanding of JTAG & BSDL standards
Good understanding on Test clocking requirements, Test mode timing closure

Job Responsibility

DFT Architecture definitions for SoC development
Leading complex activities and providing solutions for complex DFT problems
Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs
Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies
Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs
Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology

Fulltime

Senior Signal Delivery Engineer

We are seeking a Senior Signal Delivery Engineer to join the Teradyne Innovation...

Location

United States , North Reading

Salary:

166300.00 - 266100.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or related field
Minimum 7 years of experience in signal integrity or high-speed hardware design
Proven experience with signal delivery in advanced semiconductor systems
Strong working knowledge interconnect standards
Experience working with microbump technology and its impact on signal integrity
Familiarity with fine pitch probing techniques and associated challenges
Proficiency in simulation tools such as Ansys HFSS, SIwave, ADS, or equivalent
Experience with PCB layout tools and design for signal integrity
Familiarity with lab equipment for signal validation (oscilloscopes, TDR, VNA)
Strong analytical and problem-solving skills

Job Responsibility

Lead the design and analysis of high-speed signal delivery systems supporting high speed industry data interfaces such as PCIe, UCIe, etc.
Develop simulation models and perform signal integrity analysis to ensure robust performance across various operating conditions
Collaborate with cross-functional teams including packaging, PCB layout, and silicon design to optimize signal paths and microbump connections
Build and validate prototypes to test signal delivery performance and compliance of system probe card interfaces including microbump and fine pitch probing specifications
Support product development from concept through production, ensuring signal integrity and reliability
Ensure compliance with industry standards and internal quality metrics
Drive PCB design efforts involving very large panels, high layer count sequential builds, and fine pitch sequential lamination
Lead development of ultra-fine pitch MLO (Multi-Layer Organic) substrates with embedded active and passive components
Coordinate and manage cross-site, global engineering teams to ensure alignment and execution across time zones
Provide clear, data-driven risk assessments and mitigation strategies to management and stakeholders

What we offer

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more
This job is eligible for discretionary bonus(es) based on financial performance

Fulltime

Senior Manager Silicon Design Engineering

AMD

Location:
Malaysia , Penang

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
February 13, 2026

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Senior Manager Silicon Design Engineering

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Location:Malaysia , Penang

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Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:February 13, 2026

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Location:
Malaysia , Penang

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Job Posted:
February 13, 2026