Senior Manager, Asic Engineering Job at Hewlett Packard Enterprise (Sunnyvale)

Senior Manager - ASIC Development Engineering

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.Tech / M.Tech / Phd in Electronics, Computer science or Electrical Engineering
Minimum 14+ years of experience in DFT
Strong understanding of DFT Architecture
Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology
Proven track record of driving DFT architecture in complex ASIC designs
Work independently on multiple complex DFT problems across different projects
Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs)
Proficiency in SCAN, MBIST implementation
Solid understanding of JTAG & BSDL standards
Good understanding on Test clocking requirements, Test mode timing closure

Job Responsibility

DFT Architecture definitions for SoC development
Leading complex activities and providing solutions for complex DFT problems
Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs
Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies
Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs
Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology

Fulltime

Senior Manager - ASIC Development Engineering

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.Tech / M.Tech / Phd in Electronics, Computer science or Electrical Engineering
Minimum 14+ years of experience in DFT
Strong understanding of DFT Architecture
Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology
Proven track record of driving DFT architecture in complex ASIC designs
Work independently on multiple complex DFT problems across different projects
Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs)
Proficiency in SCAN, MBIST implementation
Solid understanding of JTAG & BSDL standards
Good understanding on Test clocking requirements, Test mode timing closure

Job Responsibility

DFT Architecture definitions for SoC development
Leading complex activities and providing solutions for complex DFT problems
Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs
Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies
Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs
Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology

Fulltime

Senior Program Manager

As a SoC Program Manager, you will lead end-to-end execution across complex Syst...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Must have experience in SoC/ASIC product cycles and understanding of architecture, integration, validation, and silicon bring-up phases
Strong familiarity with SoC / IP execution flows: Architecture to tapeout lifecycle (standard RTL and netlist-based milestones), IP integration and dependency management, Pre-silicon and post-silicon execution flows, System-level bring-up and platform readiness
Detail-oriented, self-driven with a strong sense of pride and ownership
Proficiency in project management tools (JIRA, Confluence, PowerBI, Excel, MS Project, AI tools)
Strong organizational, problem-solving, interpersonal, presentation, written and verbal communication skills
Ability to build relationships and work effectively as a self-starter and as part of a team
Prior experience driving large multi-site or multi-vendor engagements is desirable
People management experience is desirable
Excellent verbal and written communication skills
Horizontal leadership/Matrix management experience

Job Responsibility

Lead end-to-end execution across complex System-on-Chip (SoC/ASIC) development programs from architecture through tapeout and post-silicon phases
Drive program milestones, manage cross-functional dependencies across IP teams (CPU/GPU/NOC/DDR/SoC subsystems), and ensure alignment across RTL, PD, DFT, firmware, validation, and platform teams
Be responsible for planning, tracking, reporting, and risk management across all phases of SoC execution
Ensure predictable delivery and high-quality outcomes
Define, structure, and drive end-to-end SoC program plans
Ensure requirements are clearly defined and integrated into design, validation, and silicon execution plans
Create and maintain detailed schedules
Track progress across IP teams and ensure timely milestone completion
Drive disciplined execution through structured action tracking, meeting cadences, and program reviews
Drive milestone checklist compliance and readiness reviews

What we offer

Benefits offered are described: AMD benefits at a glance

Fulltime

Senior Program Manager

As a SoC Program Manager, you will lead end-to-end execution across complex Syst...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Must have experience in SoC/ASIC product cycles and understanding of architecture, integration, validation, and silicon bring-up phases
Strong familiarity with SoC / IP execution flows
Architecture to tapeout lifecycle (standard RTL and netlist-based milestones)
IP integration and dependency management
Pre-silicon and post-silicon execution flows
System-level bring-up and platform readiness
Detail-oriented, self-driven with a strong sense of pride and ownership
Proficiency in project management tools (JIRA, Confluence, PowerBI, Excel, MS Project, AI tools)
Strong organizational, problem-solving, interpersonal, presentation, written and verbal communication skills
Ability to build relationships and work effectively as a self-starter and as part of a team

Job Responsibility

Lead end-to-end execution across complex SoC/ASIC development programs from architecture through tapeout and post-silicon phases
Drive program milestones, manage cross-functional dependencies across IP teams
Ensure alignment across RTL, PD, DFT, firmware, validation, and platform teams
Plan, track, report, and manage risk across all phases of SoC execution
Define, structure, and drive end-to-end SoC program plans
Ensure requirements are clearly defined and integrated into design, validation, and silicon execution plans
Create and maintain detailed schedules
Track progress across IP teams and ensure timely milestone completion
Drive disciplined execution through structured action tracking, meeting cadences, and program reviews
Drive milestone checklist compliance and readiness reviews

What we offer

Benefits offered are described: AMD benefits at a glance

Vlsi Design Verification Manager - Slingshot Asic Team

Hewlett Packard Enterprise is seeking a VLSI Design Verification Manager to lead...

Location

United States , Ft. Collins

Salary:

142000.00 - 270000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent
Typically 10+ years of experience in VLSI design verification, with strong hands-on background in pre-silicon DV
Strong understanding of SystemVerilog and UVM-based verification methodologies
Demonstrated technical leadership in design verification
Ability to lead engineers through influence, technical credibility, mentorship, and clear communication
Experience with verification planning, coverage-driven verification, regression management, and sign-off readiness
Proficiency with DV workflows using industry EDA simulation tools
Strong analytical and problem-solving skills
Excellent written and verbal communication skills
Ability to operate effectively in a multi-site, cross-functional engineering environment

Job Responsibility

Provide leadership and direction for a team responsible for all phases of pre-silicon design verification, including verification planning, testbench development, coverage closure, regression management, and sign-off reviews
Define, own, and evolve design verification methodology, ensuring consistent, high-quality verification practices across block, subsystem, and full-chip scopes
Ensure development of robust SystemVerilog/UVM-based environments, including stimulus, scoreboards, checkers, assertions, and functional coverage
Drive regression health, failure triage, root-cause isolation, and closure of design issues in close collaboration with logic design and architecture teams
Manage project deliverables, schedules, and staffing to meet program milestones and quality goals
Recruit, mentor, and develop engineers
set performance expectations and support career growth across junior through senior levels
Identify and drive opportunities for process improvement, reuse, automation, and efficiency in verification workflows
Communicate verification status, risks, and readiness clearly to management and cross-functional partners

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Senior Engineer - ASIC Backend Synthesis

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an P...

Location

India , Bangalore

Salary:

Not provided

Ericsson

Expiration Date

Until further notice

Requirements

8+ years in physical synthesis or logic design implementation
Expert-level use of Fusion Compiler
Strong SDC constraint authoring and management skills
Experience with physical-aware synthesis flows and P&R hand-off
Working knowledge of STA (PrimeTime)
Proficiency in Tcl
Python scripting a strong plus
At least one tape-out on 7nm or below
B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field
Strong foundation in digital logic design, CMOS circuit theory, and standard-cell library concepts

Job Responsibility

Physical-Aware Synthesis (PAS)
Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises
Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing
Collaborate with P&R engineers on DEF/floorplan hand-off
iterate on netlist quality to reduce downstream ECO effort
Perform flat and hierarchical synthesis for large designs
manage partitioning and interface timing budgets
Perform formal or equivalence check on the netlist at block or top level
QoR & Optimization
Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners

Fulltime

Senior FPGA ASIC Design Engineer

Join a team at the forefront of computing innovation. This is an exceptional opp...

Location

United Kingdom , Penicuik

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience with modern, complex digital processing architectures
Deep understanding of FPGA and ASIC design flows, tools, and system-level design
Solid software development and integration skills
A proven track record of technical leadership, mentoring engineers, and driving projects from concept to delivery

Job Responsibility

Lead technical discussions and collaborate with system architects, hardware, and software engineers to define and deliver new features
Act as a technical mentor to junior engineers through design reviews, best-practice guidance, and day-to-day support
Design and implement high-quality, high-performance RTL for new features, modules, and systems
Develop software and scripts to configure, control, and test hardware modules and systems
Create clear, detailed documentation describing designs and interactions with hardware and software components
Debug complex system-level issues, identify root causes, and partner with verification teams to deliver robust solutions
Estimate development schedules and test-environment needs, and support junior engineers with project planning
Champion continuous improvement in design, validation, and development workflows
Take on increasing leadership responsibilities, with a clear path toward senior technical or team management roles

Fulltime

Senior Manager-ASOC

We are starting a new Silicon R&D center in Bangalore. Join our team as we pione...

Location

India , Bangalore

Salary:

Not provided

Ericsson

Expiration Date

Until further notice

Requirements

Bachelor’s degree in electrical or computer engineering
Proven leadership experience in all the following areas - Team management (at least 3 years) building a motivated, innovative and empowered team
Coaching and mentoring
Written and verbal communications and presentations
Ability to build on cultural diversity and collaborate across teams, organizations and sites
Agile ways of working and project management
10+ years’ experience as an individual contributor designer or verifier
Experience with GIT, and Synopsys tools like Spyglass
Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results
High attention to detail and commitment to quality

Job Responsibility

Driving Execution within Backend Development & Physical Implementation team responsible of Perform synthesis, constraint development, equivalence checking, and place-and-route for advanced digital ASICs
Drive static timing analysis (STA) and support timing sign‑off activities
Optimize timing, area, and power
ASIC Top Level Verification (TLV/SoC verification) team responsible of SoC level testcase development with possibilities to specialize in special areas related to traffic on external interfaces and/or ASIC internal functionality involving DSPs, MCUs, CPU cores, ARM infrastructure, switches, security, SerDes, DDR and other types of external memory and much more
Preparing and setting up designs to run in Hardware Emulators, and update and maintain existing emulator platforms
Act as an interface towards stakeholders and vendors
Ensure good collaboration with other teams both on-site and cross-site
Recruit and develop team designers and verifiers
Manage individual and team performance
Develop a motivating, customer oriented and exciting work environment

What we offer

International work environment with opportunities for professional growth and development
Collaborative and inclusive culture that values diversity and innovation
Competitive compensation and benefits package
Work-Life Balance
Professional Growth

Fulltime

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Senior Manager, Asic Engineering

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