Senior Manager, ASIC Engineering Job at Hewlett Packard Enterprise (San Jose)

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical i...

Location

United States , Batavia, Illinois

Salary:

Not provided

NHanced Semiconductors

Expiration Date

Until further notice

Requirements

US Citizenship
5+ years of experience in physical design, specifically in ASIC, SoC, or advanced packaging (2.5D, 3DIC) technologies
Hands-on experience with Git-based version control systems for managing design revisions
Experience with timing closure and signal integrity
Proficiency in Cadence tools for physical design, timing analysis, and signoff
Strong understanding of RTL-to-GDSII flows, including floorplanning, power planning, place-and-route, and timing closure
Working knowledge of parasitic extraction (PEX), power integrity (PI), and thermal analysis in multi-die environments
Ability to work independently with minimal supervision and drive tasks to completion
Excellent verbal and written communication skills for collaboration across engineering teams
Strong debugging skills and ability to analyze tool reports, logs, and simulation results

Job Responsibility

Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
Ensure design compliance with timing, power, and area (PPA) requirements, as well as DFM, DRC, and LVS constraints
Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff
Develop and execute timing closure strategies, working with STA engineers to meet performance goals
Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments
Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration
Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration
Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions
Utilize Git-based version control workflows for design database management and collaborative development
Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs

Technologist, ASIC Development Engineering

We are looking for a highly skilled and experienced individual for SoC PD lead p...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs
Proven ability in technically leading a small/medium-sized team for executing projects preferred
Hands-on experience on the entire PD Flow from RTL to GDSII
Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains
Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
Exposure to static timing analysis fixes including automated ECO generation
Strong in areas on CTS, Power, Bump planning, Floorplan
Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies
Library preparation in any environment (Synopsys, Cadence, etc)

Job Responsibility

To be responsible for leading RTL-to-GDSII SoC implementation effort
To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.
To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity
To ensure process compliance during project execution and enable / participate in technical discussions/reviews
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow
Foster a culture of innovation, collaboration, and continuous improvement

Fulltime

Senior Hardware Engineer

As a key contributor in the HW Sustaining group, you will be responsible for inv...

Location

United States , San Jose

Salary:

117500.00 - 270000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s degree or higher in Electrical, Electronics, or Computer Engineering
8+ years of hardware design, debug and testing experience at the board and system level
Expertise in debugging hardware problems using oscilloscopes, logic analyzers, and specialized networking test equipment such as IXIA/Spirent traffic analyzers, PCI analyzers, and in-circuit emulators
PCB design experience including schematic capture, PCB layout and routing
Familiarity with Cadence System Design tool suite
Knowledge of networking hardware and associated components and interfaces such as switch ASICs, PHY, SerDes, CPU subsystems, optics, high-speed serial links, PoE, PCIe, NVMe, SATA, I2C, and USB
Expertise in high speed circuit design and debug
Familiarity with signal and power integrity concepts and associated test and simulation tools
Ability to manage multiple concurrent priorities and make progress
Able to manage hardware debug and design projects and driving them to closure

Job Responsibility

Lead failure analysis for critical hardware issues reported from field and factory
Determine and document root cause and corrective actions (RCCA)
Extract and share 'Lessons Learned' from HW Sustaining failure analysis and share with appropriate Juniper teams to drive hardware quality improvement
Collaborate with other Engineering and Manufacturing / Operations teams to drive corrective actions and hardware quality improvements
Work with Customer Support teams to understand and address customer hardware concerns
Analyze hardware quality metrics and Repair Center findings to identify failure trends requiring investigation
Provide technical leadership into multi-sourcing and change management activities on shipping products
Review hardware test reports for new products prior to product release
Identify any quality concerns and work with the design teams to resolve
Mentor and guide junior members, foster a collaborative environment, and encourage curiosity and knowledge sharing

What we offer

Comprehensive suite of benefits that supports physical, financial and emotional wellbeing
Career development programs to help achieve career goals
Inclusive culture celebrating individual uniqueness

Fulltime

Senior Technical Marketing Engineer

As a Technical Marketing Engineer, you will develop deep knowledge of HPE's Camp...

Location

United States , Roseville

Salary:

117500.00 - 270000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Min. 10+ years of networking, security, telemetry, and automation experience
Min. 5+ years of TME experience
Security certification will be plus
Data Center certification will be plus
Excellent knowledge of Data Center Networking designs, architectures
Excellent knowledge of data center networking security, telemetry, and automation
Excellent knowledge of Data Center designs and architectures
Data Center deployment experience such as HPE or Dell EMC hyper converged solution, HPE Storage and Compute
Advanced networking knowledge such as BGP Based EVPN, EVPN-VXLAN
Advanced security knowledge such as IPsec, NAT, IDS, IPS, DDoS and NG-Firewall

Job Responsibility

Develop compelling demonstrations that best showcase HPE Aruba Networking industry-leading solutions
Serve as the Aruba Switching authority and key technical advisor for Aruba Enterprise Switching Products and Solutions
Create technical Enterprise Switching Architectures, Webinars, Videos, Documents/ Collaterals, Podcasts, Blogs, Social media posts, Presentations, Resource Guides / Playbooks, Newsletters & email blast content, Webpages, and demonstrations for our Aruba Switching platforms and solutions
Track and identify product solution gaps, competitive differentiation, and link the outputs to marketing collateral and engineering developments
Proactively learn and engage with SE/CSE/Customers, enhance knowledge and build subject-matter expertise
Reference Architectures: Create examples of use cases and network deployments, highlighting Aruba Switching’s unique value proposition and best practices
Develop 'deep-dive' technical presentations used by Aruba’s Pre-Sales Engineering team, Channel and Service Provider partners to educate customers
Reinforce Core Product Managers in writing PRDs and prioritizing Customer NFRs
Create and drive development of technical collateral to better enable sales engineers and partners
Assist System Engineers, Marketing, and Sales teams with technical presentations, roadmap updates, and product demonstrations

What we offer

Comprehensive suite of benefits that supports physical, financial and emotional wellbeing
Career development programs catered to reaching career goals
Flexibility to manage work and personal needs
Unconditional inclusion

Fulltime

Software Development Kit and Application Specific Integrated Circuit Systems Software Engineer III

Designs, develops, troubleshoots and debugs software programs for software enhan...

Location

United States , Roseville

Salary:

103400.00 - 237000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Computer Engineering, Computer Science, or equivalent
Typically, 4-6 years' experience
Extensive experience with multiple software systems design tools and languages: Real-time embedded OS, C, Rust, Go and Python
Experience to read the ASIC designs and understand them in detail
Experience working with Emulator and Simulator environments
Excellent analytical and problem-solving skills
Experience in overall architecture of software systems: Linux kernel drivers, Embedded Systems
Designing and integrating software systems running on multiple platform types into overall architecture
Evaluating forms and processes for software systems testing and methodology, including writing and execution of test plans, debugging, and testing scripts and tools
Excellent written and verbal communication skills

Job Responsibility

Designs enhancements, updates, and programming changes for portions and subsystems of systems software, including operating systems, compliers, networking, utilities, databases, and Internet-related tools
Analyzes design and determines coding, programming, and integration activities required based on general objectives and knowledge of overall architecture of product or solution
Writes and executes complete testing plans, protocols, and documentation for assigned portion of application
identifies and debugs, and creates solutions for issues with code and integration into application architecture
Leads a project team of other software systems engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for assigned systems portion or subsystem
Collaborates and communicates with management, internal, and outsourced development partners regarding software systems design status, project progress, and issue resolution
Represents the software systems engineering team for all phases of larger and more-complex development projects
Provides guidance and mentoring to less- experienced staff members

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

New

Senior Manager - ASIC Development Engineering (DFT,MBIST,SCAN)

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.Tech / M.Tech / Phd in Electronics, Computer science or Electrical Engineering
Minimum 14+ years of experience in DFT
Strong understanding of DFT Architecture
Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology
Proven track record of driving DFT architecture in complex ASIC designs
Work independently on multiple complex DFT problems across different projects
Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs)
Proficiency in SCAN, MBIST implementation
Solid understanding of JTAG & BSDL standards
Good understanding on Test clocking requirements, Test mode timing closure

Job Responsibility

DFT Architecture definitions for SoC development
Leading complex activities and providing solutions for complex DFT problems
Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs
Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies
Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs
Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology

Fulltime

Director of Engineering

We are seeking a highly experienced and strategic Director of Engineering to tak...

Location

India , Chennai

Salary:

Not provided

Arrcus

Expiration Date

Until further notice

Requirements

BS/MS/PhD in Computer Engineering/Computer Science or equivalent degree
Excellent communication, presentation, and interpersonal skills
5+ years of experience leading and managing distributed engineering teams involved in creating complex software products
10+ years of relevant experience in managing very senior technical talent in some of the following areas: Networking protocols such as OSPF, BGP, ISIS, MPLS, BFD, MLAG, EVPN, VxLAN, SR-MPLS, SRv6, L3VPN
Test Harness like Robot framework, Jinja2
Familiarity network merchant silicon chipsets and whitebox platforms
Software development of Network Data Path (Linux, virtual and ASIC)
Virtualization technologies like SR-IOV, Intel DPDK, FD.io, NSX, OVS
High Availability, ISSU, Linux networking
Debian Build/Packaging, Linux Kernel, Kernel Networking Stack

Job Responsibility

Work with customer and product teams to understand and prioritise new requirements
Develop a holistic understanding of individual employee skill sets and drive resource allocation for customer requirements
Help drive the recruiting process both in terms of attracting new talent as well as defining and streamlining the recruitment process
Continuous Process Improvement: Solicit feedback, drive discussion and implement process and workflow improvements
Provide technical guidance and mitigation for engineering projects
Build 1:1 rapport with engineers, help identify and fulfil personal aspirations by aligning with larger team goals
Strong ability to plan, execute and deliver multiple projects across worldwide sites
Experience with rapidly growing engineering organizations in all aspects of people, resources, tools, and more

What we offer

Generous compensation packages including equity
Medical Insurance
Parental Leave

Fulltime

Lead IP/SOC Verification

In this high-profile role, the Lead IP/SOC Verification will be the overall desi...

Location

United States , Folsom

Salary:

171200.00 - 256800.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Experience focused on IP and/or SOC verification with successful completion of multiple ASICs that are in production
Requires proven track record in technical leadership. This includes planning, execution, tracking, verification closure, and delivery to programs
Requires strong experience with development of UVM, SystemVerilog, C/C++ and Scripting Languages
Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
Good understanding of code and functional coverage, ability to influence coverage improvement with design and verification teams
Good understanding of requirements management, documentation management, and defect management
Ability to grasp concepts during discussions and turn minutes into action items
Able to communicate concepts and processes with stakeholders
Analytical, self-motivated, organized, detailed-oriented and results-oriented
Excellent interpersonal skills including the ability to work well with multiple people and teams, ability to communicate progress to team members on a regular basis

Job Responsibility

Closely work with designers and architect to come up with features, verification and execution plans
Own and lead verification quality for GFXIP projects
Engage with IP and SOC teams to drive closure to verification strategy
Working with architects and verification leads and driving quality test plan specifications
Collaborate with architects, hardware engineers, and firmware engineers to understand the complex features and impact to System level/SOC environment
Developing verification strategy, infrastructure and needed improvements
Driving Pre and post Si verification closure to meet schedule with quality
Leading Post Si verification activities to drive triage with FW, SW, IP, SOC and various teams. Plug holes appropriately to improve quality of the IP
Working with each domain (sub-system) lead and guide them to get better quality and verification outcome
Automating workflows in a distributed compute environment

Fulltime

Senior Manager, ASIC Engineering

Hewlett Packard Enterprise

Location:
United States , San Jose

Category:
IT - Software Development

Contract Type:
Employment contract

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
October 07, 2025

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