Senior Manager, ASIC Engineering

• Manage design & verification team for large, complex high-speed ASICs for HPE's next generation of networking products
• Technically lead a team of engineers to successfully deliver chip from specification to tapeout
• Create and maintain schedule
• Work closely with logic designers, software developers
• Mentor junior engineers with the verification flow, strategy

• BS/MS in Electrical Engineering or equivalent field
• Minimum of 10+ years of ASIC experience
• Prior engineering management experience
• Strong Verilog, SystemC or C/C++, Perl/shell scripts or Vera programming skills
• Proven leadership and communication skills
• Networking experience is highly desirable
• Track record of successfully managed/lead multiple ASIC's from start to finish
• Ability to hire, retain and develop high performance teams

Networking experience

• Health & Wellbeing benefits
• Personal & Professional Development programs
• Unconditional Inclusion environment
• Comprehensive benefits suite supporting physical, financial and emotional wellbeing