Senior FPGA / RTL Design Engineer - Signal Processing Jobs

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies (International)

Location:
United States, Irvine

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

125000.00 - 195000.00 USD / Year

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Job Description:

Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D. These are exciting projects aimed at addressing challenging real-world communication needs.

Job Responsibility:

Digital design architecting for wireless communication projects
Fixed point design of signal processing blocks while working with systems engineers
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering teams

Requirements:

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 6 years of demonstrated experience in FPGA design
4 years of FPGA design experience with a Master of Science degree
2 years of FPGA design experience with a PhD
Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
Proven expertise working with multiple clock-domain, high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts
All employment is contingent upon the successful clearance of a background check

Nice to have:

Master of Science degree in Electrical Engineering (MSEE)
Experience using MATLAB
Experience with communication systems on FPGA or ASIC designs

Additional Information:

Job Posted:
December 12, 2025

Employment Type:

Fulltime

Work Type:

Hybrid work

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