Senior Engineer, Closures Job at Archer Aviation (San Jose)

MBSE Indications and Warning Senior Systems Engineer

Arcfield is seeking a model-based Senior Systems Engineer dedicated to supportin...

Location

United States , Chantilly

Salary:

Not provided

Arcfield

Expiration Date

Until further notice

Requirements

8 to 10 years with BS/BA or 6 to 8 years with MS/MA or 3 to 5 years with a PhD in a STEM field
OCSMP certification (Level 1 or Level 2 mandatory) and willingness to obtain Level 3
Must possess and have the ability to maintain a TS/SCI w/ Poly clearance
Technical experience working with space-based sensors and systems
Knowledge of space/ground/comm systems and sensor vulnerabilities
Experience with large acquisition systems engineering efforts, methods, and processes
Ability to work well in a fast paced, dynamic environment
Good oral and written communication skills
Good business acumen
Organized and flexible

Job Responsibility

Provide technical modeling support by assessing space requirements, Concept of Operations (CONOPs), architecture products, system schedules, and risks for end-to-end closure of the baseline for Space protection-related activities in the overall Enterprise
Work collaboratively across stakeholder organizations to obtain system end-to-end closure of the Enterprise Resiliency I&W program by supporting system readiness events out of the model following approved digital engineering processes for integration and closure
Interact with several government enterprise systems engineers and stakeholders, as well as multiple Acquisition Offices (AOs) and government and contractor stakeholders to drive resolution plans and strategies for complex technical challenges
Support the Enterprise Resiliency Enterprise Portfolio Manager with strategic planning for future capability acquisition and insertion into the baseline leveraging digital tools

Fulltime

Senior Associate, Packaging Engineer

Consumer packaging is everywhere and in many cases it’s unavoidable. Packaging ...

Location

United States , New York

Salary:

90800.00 - 113500.00 USD / Year

Harry's

Expiration Date

Until further notice

Requirements

Studied/degree in Packaging Engineering and/or studies in mechanical engineering, industrial design, materials and chemical engineering and related fields. BS in Package Engineering, Mechanical Engineering, other related disciplines, or demonstrated equivalent experience
2+ years of experience in the design, testing, and development of new packaging using a range of component manufacturing processes and materials
Having knowledge of a variety of material properties and packaging components such as pumps, closures, bottles, tubes, aerosols, folding cartons, gift sets, flexible films and laminations
You have a good eye for design and aesthetics, plus experience with decorating techniques and materials used on primary and secondary packaging
Honest, direct, and ability to articulate and defend technical packaging decisions as well as communicate clearly with cross functional teams
Experience with 2D engineering drawings to define critical dimensions, and using engineering analysis methods such as Tolerance Analysis and Statistical Analysis
Experience in one 3D MCAD package (eg. Artios, Solidworks)
Extremely organized, dependable and self-motivated with the ability to excel in a hands-on, fast paced environment
Life-long learner: You love learning new things and are not afraid to admit when you don’t know an answer
Sense of humor -- we take our work seriously and ourselves un-seriously

Job Responsibility

Bring your passion and enthusiasm for package engineering to work every day
Research packaging sustainability/innovation/trends and develop packaging components that support new product introductions, retail exclusives, promotions and partnerships, and operational initiatives
Recommend and own packaging workstreams required to qualify packaging components, tooling, equipment and processes
Develop specifications as part of the package development process. Access, modify or create 3D CAD models and 2D engineering drawings to build prototype tools, samples, and approve component structures
Work with packaging component suppliers to design for manufacturing, apply robust testing plans to validate the design, and qualify production release in partnership with technical cross functional partners
Participate in and drive packaging engineering design reviews
Own packaging line trials and test plans. Troubleshoot packaging-related technical issues during development
develop risk mitigation plans and packaging alternatives
Work with the Production Artist team to develop color standards and establish production color ranges
Bring printing and decorating experience to the process of graphics design, decoration testing, and artwork approval

What we offer

Medical, dental, and vision coverage
401k match
Equity in Mammoth Brands
Flexible time off and working hours
Wellness and L&D stipends
4 weeks sabbatical after 5 years, 6 weeks after 10 years, and 8 weeks after 15 years
20 fully paid weeks off for parents who give birth, or 16 fully paid weeks off for all other paths to parenthood
Fun IRL and virtual events including happy hours, team building events, and parties on our rooftop
Free products from all of our brands

Fulltime

Senior Hardware Engineer

As a key contributor in the HW Sustaining group, you will be responsible for inv...

Location

United States , San Jose

Salary:

117500.00 - 270000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s degree or higher in Electrical, Electronics, or Computer Engineering
8+ years of hardware design, debug and testing experience at the board and system level
Expertise in debugging hardware problems using oscilloscopes, logic analyzers, and specialized networking test equipment such as IXIA/Spirent traffic analyzers, PCI analyzers, and in-circuit emulators
PCB design experience including schematic capture, PCB layout and routing
Familiarity with Cadence System Design tool suite
Knowledge of networking hardware and associated components and interfaces such as switch ASICs, PHY, SerDes, CPU subsystems, optics, high-speed serial links, PoE, PCIe, NVMe, SATA, I2C, and USB
Expertise in high speed circuit design and debug
Familiarity with signal and power integrity concepts and associated test and simulation tools
Ability to manage multiple concurrent priorities and make progress
Able to manage hardware debug and design projects and driving them to closure

Job Responsibility

Lead failure analysis for critical hardware issues reported from field and factory
Determine and document root cause and corrective actions (RCCA)
Extract and share 'Lessons Learned' from HW Sustaining failure analysis and share with appropriate Juniper teams to drive hardware quality improvement
Collaborate with other Engineering and Manufacturing / Operations teams to drive corrective actions and hardware quality improvements
Work with Customer Support teams to understand and address customer hardware concerns
Analyze hardware quality metrics and Repair Center findings to identify failure trends requiring investigation
Provide technical leadership into multi-sourcing and change management activities on shipping products
Review hardware test reports for new products prior to product release
Identify any quality concerns and work with the design teams to resolve
Mentor and guide junior members, foster a collaborative environment, and encourage curiosity and knowledge sharing

What we offer

Comprehensive suite of benefits that supports physical, financial and emotional wellbeing
Career development programs to help achieve career goals
Inclusive culture celebrating individual uniqueness

Fulltime

Senior Geotechnical Engineer – Tailings & Water Dams

Senior Geotechnical Engineer role in the Mining Environmental Group, based out o...

Location

Canada , Vancouver

Salary:

110000.00 - 160000.00 CAD / Year

Klohn Crippen Berger

Expiration Date

Until further notice

Requirements

A degree in civil or geotechnical engineering
10+ years’ experience in civil or geotechnical related projects (preferably for mining or related industries), with a track record of continued development
You must be eligible to register as professional engineer in Canada
Experience in geohazard engineering, assessments, investigations, design, tendering and construction administration
Working knowledge of geotechnical software packages including PLAXIS, FLAC, and SLOPE/W
General understanding of mining-related regulations and industry best practices
Passion for collaborating with clients and fostering long-term relationships
Demonstrated ability to work in a dynamic and fast-paced environment
Enhanced communication skills, which should include experience in writing proposals, technical reports, and general project correspondence
Experience in a safety focused environment with near miss and incident reporting requirements

Job Responsibility

Engage with clients, colleagues, and suppliers on geotechnical focused field programs and design solutions
Lead teams focused on civil / geotechnical designs for mine waste projects
Collaborate within multi-disciplinary project teams for the delivery of mine waste projects
Participate in dam safety inspections, dam safety reviews, and the development of dam safety systems
Guide, mentor, and train more junior staff in your area(s) of expertise
Build client rapport as projects progress from feasibility through to mine closure
Coordinate with other engineering disciplines to develop well rounded solutions for clients
Prepare technical reports, proposals, and other project specific documentation

What we offer

Hybrid work opportunities
Annual performance and salary review
Above average bonus payouts
Vacation policy that aligns to your experience
Paid OT, and wellness days
Flexible benefits, including RSP, social, and mental well-being initiatives

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical i...

Location

United States , Batavia, Illinois

Salary:

Not provided

NHanced Semiconductors

Expiration Date

Until further notice

Requirements

US Citizenship
5+ years of experience in physical design, specifically in ASIC, SoC, or advanced packaging (2.5D, 3DIC) technologies
Hands-on experience with Git-based version control systems for managing design revisions
Experience with timing closure and signal integrity
Proficiency in Cadence tools for physical design, timing analysis, and signoff
Strong understanding of RTL-to-GDSII flows, including floorplanning, power planning, place-and-route, and timing closure
Working knowledge of parasitic extraction (PEX), power integrity (PI), and thermal analysis in multi-die environments
Ability to work independently with minimal supervision and drive tasks to completion
Excellent verbal and written communication skills for collaboration across engineering teams
Strong debugging skills and ability to analyze tool reports, logs, and simulation results

Job Responsibility

Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
Ensure design compliance with timing, power, and area (PPA) requirements, as well as DFM, DRC, and LVS constraints
Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff
Develop and execute timing closure strategies, working with STA engineers to meet performance goals
Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments
Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration
Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration
Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions
Utilize Git-based version control workflows for design database management and collaborative development
Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs

Senior Embedded Software Engineer

The Senior Embedded Software Engineer role focuses on developing high-quality em...

Location

Singapore , Central Singapore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or equivalent
Minimum of 6 years’ experience in a relevant role
Strong programming experience in C and Python
Embedded Linux systems programming experience, including experience with the Linux Kernel, device drivers, device tree, and Yocto
Possess working knowledge of embedded software development in an RTOS environment, Board Support Package (BSP), Device Drivers
Experience with software development tools and processes, including Git or comparable revision control software
A Self-motivated, eager, and quick learner with good analytical and problem-solving skills with a passion for technology
A strong team player, able to collaborate and work with global and cross-functional teams

Job Responsibility

Develop in-depth knowledge of modules/sub-modules on-the-job and become a Subject-Matter-Expert
Provide guidelines and documentation for owned modules/sub-modules for others to follow and adhere to
Understand and gather project requirements, design modules/sub-modules, and conduct investigations accordingly
Collaborate with others to ensure smooth board bring-up
Debug any issues observed and derive fixes, also drive issue closure with relevant parties
Actively participate in technical discussions, enable decision-making, and drive progress
Proactively engage others directly in discussions whenever necessary
Articulate technical proposals/justification/issues and provide clear technical updates to project and management teams regularly on progress
Coach and support team members in their deliverables
Accountable for the highest quality delivery of our work for all our products

What we offer

Comprehensive suite of benefits supporting physical, financial and emotional wellbeing
Specific programs to help reach career goals
Inclusive work environment celebrating individual uniqueness

Fulltime

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Direc...

Location

United States , Irvine

Salary:

125000.00 - 195000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 6 years of demonstrated experience in FPGA design
4 years of FPGA design experience with a Master of Science degree
2 years of FPGA design experience with a PhD
Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
Proven expertise working with multiple clock-domain, high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Digital design architecting for wireless communication projects
Fixed point design of signal processing blocks while working with systems engineers
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering teams

Fulltime

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

5+ years of ASIC and/or physical design flow development experience
Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
Scripting experience with Python, Tcl, or Perl
Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design

Job Responsibility

Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Fulltime

Senior Engineer, Closures

Archer Aviation

Location:
United States , San Jose

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
March 10, 2026

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