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Senior Digital IC Design Engineer

France, Paris · Job Posted February 14, 2026
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Job Description

SCALINX’s design team is seeking a dynamic and experienced digital designer who will contribute to the chip/block level architecture definition and implementation. In this role, the candidate will technically drive digital work-packages to deliver a state-of-the-art Integrated Circuit (IC) in deep-submicron CMOS technologies.

Job Responsibility

  • Design of complex RTL blocks based on micro-architecture specifications
  • Top level integration of various RTL blocks and complex IPs
  • Execute complete LINT/CDC/RDC checks
  • Write SDC constraints to run logical synthesis
  • Write detailed design documentation in accordance with company QA policy
  • Generates KPI and report progress to the Program Manager
  • Timely deliver state-of-the-art RTL package to Digital Verification, DFT and Back-End teams
  • Lead and support digital design work-packages from RTL to netlist
  • Animate design reviews
  • Participate with the other project technical leaders in the definition of the IC architecture specifications and verification methodology
  • Contribute, in close collaboration with the DFT and Back-End team, to the physical implementation of the IC digital blocks to achieve the best area/power trade-off
  • Contribute to the test and verification strategy
  • Participate to the evaluation of the manufactured IC in our measurement lab
  • Work as a team player to successfully deliver a state-of-the art IC

Requirements

  • MSc or PhD in Electrical Engineering or equivalent
  • Very good understanding of the entire digital IC design flow from RTL to GDSII
  • Strong expertise in digital electronics and signal processing
  • Proven experience in digital IC projects and technical leadership roles
  • Strong experience with ARM or RISC-V based SoC platform design
  • Solid experience with high-speed serial interfaces (JESD204, Ethernet, PCIe…)
  • Expertise in digital hardware description languages (VHDL or Verilog) and SystemVerilog
  • Experience with Cadence, Synopsys or Siemens RTL design flow
  • Proven experience with GIT and Linux systems
  • Skilled in scripting languages (Python, TCL, Perl)
  • Fluent communication in English (oral and written)

Nice to have

  • Experience with multi-clock domain and power efficient designs is a plus
  • Previous experience with Analog Mixed-Signal designs
  • Experience in design and verification of A/D Converters, D/A Converters, and/or RF transceivers is a plus

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