Senior Dft Engineer Job at AMD (Bangalore)

New

Senior DFT Engineer

As a member of the Radeon Technologies Group, you will help bring to life cuttin...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Implementation and verification of DFT architecture and features
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Fulltime

Senior Engineer - Design for Test (DFT)

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
equivalent experience
4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test
ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check

Job Responsibility

Own block level DFT u-arch specification documentation & provide Test solutions in design for test chips and products
Ensure DFX goals (testability, debug, manufacturability, System Test, System Debug, Repair) are met by these IPs, ensure analog to digital boundaries are reliably tested. Review coverage metrics for Digital logic
Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI
Provide test plans and engage closely with verification engineers to perform waveform reviews
Ensure RTL quality pre-DFT to ensure the RTL is good for DFT insertion and coverage
Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis
Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (Architects, front-end & back-end design/verification, Physical design, and post-silicon manufacturing) with respect and with One Microsoft mentality to establish synergies

Fulltime

Senior Engineer, ASIC Development Engineering

As a SoC Validation/Verification Engineer, you will play a key role in ensuring ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or MS degree in Electrical Engineering or Computer Engineering
4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up
Deep understanding of C, embedded programming, and hardware/software co-validation methodologies
Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts
Proven history of developing and executing verification and validation strategies for complex SoCs
Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB
Run complex SoC verification and validation scenarios on Palladium/Emulation platforms
Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components
Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis
Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases

Job Responsibility

Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation
Independently developing and executing tests for verification and validation
Collaborating with cross-functional teams to drive closure of verification and validation activities
Signing off on verification and validation deliverables
Debugging and root cause analysis of issues found during validation
Developing and maintaining automated test environments and regression suites
Contributing to the continuous improvement of verification methodologies and best practices
End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure

Fulltime

Senior Engineer - Verification

We are seeking skilled SoC (System-on-Chip) ARM Power architecture, Soc clock an...

Location

India , Noida

Salary:

Not provided

ARM

Expiration Date

Until further notice

Requirements

3 - 6 years of proven experience in working on SoC verification environments across Power verification involving multiple power islands and clock and reset verification
Knowledge of assembly language (preferably ARM), C/C++ and hardware verification languages (e.g. SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.)
Experience in one or more of various verification methodologies – UVM/OVM, formal, low power
Good knowledge and working verification experience in Arm M class CPU Processors
Good experience in handling Power aware verification with complex power architecture
Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation and support
Understanding of the fundamentals of Arm system architectures
Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools, UPF, and Debuggers
Experience in working and debugging Soc in DFT mode
Exposure to various front-end verification tools - Questa, VCS, Jasper Gold, Verdi

Job Responsibility

Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules
Responsible for leading a team of engineers to own and power, clk/rst verification for a complex IoT chip
Collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development and build a functional verification strategy
Senior engineers are also encouraged to support mentor junior team members

What we offer

Health and Wellness
Work and Life Success
Financial Rewards
Development and Support

New

Senior Test Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable

Job Responsibility

Responsible for product and engineering activities supporting new product development and manufacturing, with primary focus on scan (structural) test
Contribute to silicon bring-up, validation, and manufacturing readiness while working closely with cross-functional partners
Support semiconductor IC development across fabrication, manufacturing test, and packaging phases
Contribute to ATE test program development, including scan pattern integration, test method implementation, bring-up, silicon characterization, debug, and yield analysis for logic defects
Execute defined test plans and methodologies while identifying issues and escalating risks with clear technical data
Apply working knowledge of Design-for-Test (DFT), including scan architecture, ATPG, fault models, silicon fabrication processes, product qualification and reliability, and basic transistor theory
Collaborate with design, DFT, product, and manufacturing teams to support scan test readiness, coverage closure, and issue resolution
Gain exposure to product domains such as high-performance computing, AI, GPUs, and telecom, as applicable to assigned projects
Apply industry-standard DFT features, including scan (SAF/TDF), JTAG, boundary scan, and at-speed testing
Support scan test content generation, including ATPG pattern validation, pattern bring-up, and post-silicon debug activities

Fulltime

Asic / Physical Design Engineer (Int, Senior and Principal)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

8+ years in ASIC Physical Design / Backend Implementation (PnR)
End-to-end experience from netlist to GDSII (full physical design flow)
Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
Proven timing closure expertise (setup/hold, ECO implementation)
Deep experience with Synopsys and/or Cadence tool suites
Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
Strong Static Timing Analysis (STA) and timing report analysis
Experience with clock tree synthesis (CTS) and clock optimization
Solid understanding of DRC/LVS and physical verification flows
IR drop / power integrity analysis and optimization experience

Fulltime

Senior Hardware Engineer

We are seeking an experienced and talented Senior Hardware Engineer to be part o...

Location

United States , Hoboken

Salary:

Not provided

Quantum Computing Inc.

Expiration Date

Until further notice

Requirements

Bachelor of Science (BS) in Electrical Engineering or Computer Engineering (EE or CE) from an accredited university
BS in EE or CE and 6+ years of experience or MS EE or CE with 4+ years of experience
Proven experience designing PCBs from schematic capture, layout design, and review
Experience with at least one ECAD suite (Altium, OrCAD, Allegro, CircuitMaker, or others) Altium is strongly preferred
Familiarity with PCB design best practices related to Signal Integrity, Power Integrity, and EMI/EMC compliance
Strong foundation in PCB design related to DFM, DFT, and DFA best practices
Strong electrical engineering fundamentals in Analog, Power, and Digital Electronics
Advanced experience with voltage regulators, LDO, and switch mode power supplies (SMPS)
Experience with analog electronics design (op-amps, TIAs, filters, etc.)
Experience with digital electronics design (Logic Gates, Flip Flops, Microcontrollers, RAM, ROM, Flash, etc.)

Job Responsibility

Support the development of several platforms based around classical and quantum photonics as a senior hardware engineer
Work alongside other hardware engineers to design custom electronics using Altium Designer
Evaluate critical component performance via board-level and system-level lab testing (ADCs, DACs, FPGAs, TDCs, etc.)
Work with firmware engineers, software engineers, and quantum scientists during various phases of lab testing
Work with contract manufacturers during manufacturing phases to procure custom electronics, addressing and mitigating any necessary design changes along the way
Validate the performance of custom electronics with lab testing
Document any issues uncovered during testing
Maintain documentation expected at milestone events during the entire design cycle (theory of operations, manufacturing documentation, validation testing results, etc.)
Integrate hardware into the complete system by working closely with mechanical, firmware, and FPGA engineers

Fulltime

Senior Electrical Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Redmond

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Master's Degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field AND 5+ years technical engineering experience
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Preferred: BS / MS in Electrical/Computer Engineering or equivalent industry experience
5+ years’ experience designing board and system level server products
5+ years’ experience developing board and system level bring-up and test plans
5+ years’ experience debugging board and system level issues for Cloud Servers
5+ years’ experience architecting, implementing, and validating RTL code for CPLD/FPGA system management

Job Responsibility

Understand customer requirements and high-level architectural design, execute electrical design at board level and system level, responsible for detailed design specifications
Collaborate with internal design team (thermal, mechanical, firmware, OS) and external partner (ODM/OEM) for design implementation, ensure product functionality, performance, quality and reliability
Perform complete and deep design review, including schematics, board files, BOM, DFT, DFM, etc.
Define board level bring-up and electrical test requirements, ensure complete coverage, execute or guarantee execution
Work with partner teams to create system level bring-up and end-to-end validation test plans, ensure complete coverage, guarantee execution
Troubleshooting, issue triage, leading hardware related debug efforts with partner teams, drive resolution and bug reports
Architect and implement RTL (Register-Transfer Level) code for Programmable Logic Devices (PLDs), ensuring robust and scalable hardware logic aligned with system-level requirements
Define and design computer boards and system-level solutions, including power and reset sequencing for high-performance platforms
Develop, review, and deploy comprehensive testbenches and randomized verification environments to validate CPLD logic and ensure functional integrity across edge cases

Fulltime

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Senior Dft Engineer

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