Senior Dft Engineer

• Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology
• Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows
• Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS
• Writing and maintain DFT documentation and specifications
• Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design
• Performing scan insertion, ATPG verification and test pattern generation
• Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis

• 6 years of DFT design, integration, verification, ATPG and Silicon Debug experience
• Demonstrated technical leadership and works well with cross-functional teams
• Excellent communication and interpersonal skills
• Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design
• Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc
• Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential
• Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
• Experience in solving logic design or timing issues with integration, synthesis and PD teams
• Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl)
• Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis
• Strong problem-solving skills
• Team player with strong communication skills
• Bachelors or Masters degree in computer engineering/Electrical Engineering

Knowledge of ATE and digital IC manufacturing test is a plus