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Senior Design Verification Engineer – Security IP

India, Bangalore Employment contract · Job Posted June 03, 2026
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Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The role: An RTL Design Verification Engineer role in our Security IP (SECIP) development team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our verification engineers will work on block level functional verification and its closure, and/or on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.

Job Responsibility

  • Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure
  • Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
  • Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure
  • Participate in MP subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems
  • Debug and solve integration issues with SoC Integration and SoC DV teams
  • Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members
  • Provide project execution leadership in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting if as advanced level team members

Requirements

  • BSc with a minimum of equivalent 5 years relevant experience
  • or MSc with a minimum of equivalent 3 years
  • or PhD in a directly related research area and a minimum of 1 year
  • A minimum of equivalent 10 years relevant experience if as advanced level team members
  • Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge of applicable state-of-art verification methodology and best practices, if as advanced level team members
  • Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile)
  • Proven skills in creating UVC and other UVM components. Experience with C-DPI and Formal Verification techniques are valuable assets
  • Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
  • Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc.
  • Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates
  • Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
  • Master's Degree preferred

Nice to have

  • Experience with C-DPI and Formal Verification techniques
  • Master's Degree preferred
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