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As a member of the System Architecture team at Palo Alto Networks, you will work on the development of ASICs, FPGAs and Systems that power Palo Alto Network’s Next Generation Firewall platforms. You will work on cutting edge system architectures for next generation firewall products, identify performance bottlenecks and solutions, design and model protocol and sub-component offload solutions. In addition to high level design work, you will also do hands-on coding.
Job Responsibility:
Work on the development of ASICs, FPGAs and Systems that power Palo Alto Network’s Next Generation Firewall platforms
Work on cutting edge system architectures for next generation firewall products, identify performance bottlenecks and solutions, design and model protocol and sub-component offload solutions
Prototyping and modeling of new architectures and designs
Architectural models, test infrastructure, pre- and post-silicon validation
In-house Processor Tool Chain Development - Assembler, Debugger, Simulator Infrastructure to support ASIC team development and verification
ASIC microcode and device driver development
Requirements:
Be part of System Architecture team defining the architecture of next generation ASICs, FPGAs and systems
Background in embedded networking, forwarding or platform software
Expertise with various aspects of system software design, networking protocols, multi-processor systems, and hardware offloading
In-depth knowledge of networking equipment & architectures – system hardware, CPUs, ASIC etc.
Experienced in networking protocols – mobile, routing, transport layer, SSL/TLS, etc.
Experienced in Software and Hardware co-design and understanding HW offload including system modeling for feasibility and tradeoffs
Experience with designing system software for enterprise networking equipment
Strong coding skills including C/C++, Bash, Python, etc.
Familiarity with containerized development and docker and Linux/Kernel drivers
Experience with network security desired
Familiarity with x86, MIPS and ARM architectures, and interface standards such as PCIe
Experience with IPC mechanisms and multi-CPU architectures