Senior ASIC-FPGA Verification Engineer Job at Boeing (Bengaluru)

Senior ASIC-FPGA Verification Engineer

Boeing

Location:
India , Bengaluru

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Not provided

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Job Description:

At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Boeing India Engineering seeks a Senior ASIC-FPGA Verification Engineer with considerable experience in design to support multiple product lines in commercial and defense electronics development.

Job Responsibility:

Use high-level architectural documentation along with algorithm description and implement functions for test bench architecture and test plan using UVM for IP, Subsystem and System level verification
Develop reusable testbench components like scoreboards, checkers, reference models along with UVC using SV and UVM
Own quality of deliverables for verification across multiple milestones for FPGA/ASIC life cycle
Architect Reusable Verification components, which can be used across FPGA/ASIC life cycle
Lead, drive and collaborate technical reviews with Validation, Design and System Architecture cross functional teams
Support Architecture exploration at system level using System C or TLM models using SV-UVM
Verification Domain expert for PCIe and Ethernet protocols
Identifies, tracks and status technical performance measures to measure progress and ensure compliance with verification requirements
Develop Junior engineers, solve simple to complex technical problems in verification
Support in Technical strategy in collaboration with Engineering management for the FPGA/ASIC V&V
Should lead AI initiatives for Verification Automation and Verification Reviews

Requirements:

Bachelor degree in Engineering, Engineering Technology (including Manufacturing Technology, Micro Electronics, VLSI/CAD/Embedded systems), Computer Science, Data Science, Mathematics, Physics, Chemistry, or non-US equivalent qualifications directly related to the work statement
13 to 17 years of experience in Digital Functional verification for both ASIC and FPGA at IP, Subsystem and System level as a Lead or Verification Architect
8+ years of experience in leading and owning verification Activities for Multiple ASIC and FPGA product Tape outs
7+ years of experience in Developing and mentoring Verification engineers
5+ years of Hands-on domain experience on PCIe (Transaction layer) and Ethernet (Mac Layer)
Multiple Verification tape out experience in ASIC and FPGA products
5+ years of experience in doing UVM based Testbench Architecture for PCIe and Ethernet across IP/Subsystem and system level for multiple projects in ASIC and FPGA

Nice to have:

Experience in leading Verification team for complex Ip, Subsystem and system along with Verification Architecture for ASIC and FPGA Products
Experience identifying, tracking, and providing status of technical performance metrics to measure progress and ensure compliance with requirements
Experience directing a team of engineers for technical excellence
Expert in using object-oriented programing in System Verilog along with UVM methodology
Expert in using Universal Verification Methodology (UVM): Experience crafting drivers, monitors, predictors, coverage model and scoreboards and UVCs
Expertise in verification working with internal/external VIPs, its development and evaluation with multiple vendors
Expert in crafting SVA -Assertions for dynamic simulation and formal verification
Expert in coverage (code and functional) signoff, by reviewing complex ASIC and FPGA RTL code
Work experience using Linux or Unix terminal commands
Experience using scripting languages: Make, Perl, Python, shell scripts, etc
Experience using Revision Control Systems: Subversion (SVN), CVS, Git
Experience in deriving digital ASIC and FPGA verification requirements specification from higher-level (system or board-level) requirements specifications
Experience in Power aware simulation debug with along Gate level simulation debug
Experience in Avionics protocols is a plus
Experience in DO -254 for ASIC /FPGA is a plus

What we offer:

Competitive base pay and incentive programs
Industry-leading tuition assistance program pays your institution directly
Resources and opportunities to grow your career
Up to $10,000 match when you support your favorite nonprofit organizations
Relocation based on candidate eligibility

Additional Information:

Job Posted:
March 23, 2026

Expiration:
April 04, 2026

Employment Type:

Fulltime

Work Type:

Hybrid work

Boeing - All Job Offers

Job Link Share:

Senior ASIC-FPGA Verification Engineer

Boeing

Location:
India , Bengaluru

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
March 23, 2026

Expiration:
April 04, 2026

Looking for more opportunities? Search for other job offers that match your skills and interests.

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Job Description:

Job Responsibility:

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Nice to have:

Additional Information:

Job Posted:March 23, 2026

Expiration:April 04, 2026

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