CrawlJobs Logo
Hewlett Packard Enterprise Logo Hewlett Packard Enterprise · IT - Software Development

Senior ASIC Design Verification Engineer

India, Bengaluru Employment contract · Job Posted May 04, 2026
Apply Position
Job Link Share

Job Description

Drive advanced verification using UVM methodology to validate complex ASIC features. Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM. Define, design, and execute verification plans and test suites for ASICs. Perform verification using simulation tools (VCS / NC-Sim or equivalent). Own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off. Perform functional coverage, code coverage, and gate-level simulations (GLS). Collaborate with RTL designers for debugging and software teams for bring-up and validation. Enhance verification infrastructure through automation using Perl, Python, or Shell scripting.

Job Responsibility

  • Drive advanced verification using UVM methodology to validate complex ASIC features
  • Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM
  • Define, design, and execute verification plans and test suites for ASICs
  • Perform verification using simulation tools (VCS / NC-Sim or equivalent)
  • Own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off
  • Perform functional coverage, code coverage, and gate-level simulations (GLS)
  • Collaborate with RTL designers for debugging and software teams for bring-up and validation
  • Enhance verification infrastructure through automation using Perl, Python, or Shell scripting

Requirements

  • 15+ years of experience in ASIC Verification using SystemVerilog
  • Strong expertise in UVM (preferred), OVM, or VMM methodologies
  • Experience in constrained-random verification
  • Hands-on experience with ASIC debugging and problem-solving
  • Proficiency with simulation tools like VCS / NC-Sim
  • Strong scripting skills in Perl / Tcl (Python is a plus)
  • Exposure to networking protocols (e.g., Ethernet) is desirable
  • Demonstrated technical leadership and ownership mindset
  • B.E/B.Tech or M.E/M.Tech in Electronics or related field

Nice to have

  • Python is a plus
  • Exposure to networking protocols (e.g., Ethernet) is desirable

What we offer

  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
Hewlett Packard Enterprise - All Job Offers

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Suggested Tags: Frontend Developer Secretary Talent Manager Salesforce Administrator Data Analyst
Similar Jobs for

Senior ASIC Design Verification Engineer

8 matching positions

Senior Staff Silicon Design Engineer (Design Verification)

At AMD, our mission is to build great products that accelerate next-generation c...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong experience in ASIC/SoC design
  • Strong hands-on verilog development experience, familiar with scripting languages like Perl
  • Good experience on complicate hub,control IP design
  • Strong problem solving, independent thinking, teamwork and communication skills
  • Bachelor or Master degree in E&E or Computer Engineering. (Preferred Master Degree)
Job Responsibility
Job Responsibility
  • Own part of IP feature design with cooperation with other designers
  • As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
  • The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
  • Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.
What we offer
What we offer
  • AMD benefits at a glance.
Read More
Arrow Right

Senior Design Verification Engineer – Security IP

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great pro...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BSc with a minimum of equivalent 5 years relevant experience
  • or MSc with a minimum of equivalent 3 years
  • or PhD in a directly related research area and a minimum of 1 year
  • A minimum of equivalent 10 years relevant experience if as advanced level team members
  • Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge of applicable state-of-art verification methodology and best practices, if as advanced level team members
  • Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile)
  • Proven skills in creating UVC and other UVM components. Experience with C-DPI and Formal Verification techniques are valuable assets
  • Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
  • Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc.
  • Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates
Job Responsibility
Job Responsibility
  • Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure
  • Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
  • Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure
  • Participate in MP subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems
  • Debug and solve integration issues with SoC Integration and SoC DV teams
  • Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members
  • Provide project execution leadership in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting if as advanced level team members
  • Fulltime
Read More
Arrow Right

Senior Design Verification Engineer – Graphics & Multimedia IP

The focus of this role is to plan, build, and execute the verification of new an...
Location
Location
India , Hyderabad
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proficient in IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches and working in Linux and Windows environments
  • Experienced with Verilog, System Verilog, C, and C++
  • Graphics pipeline knowledge
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Job Responsibility
Job Responsibility
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed and random verification tests
  • Debug test failures to determine the root cause
  • work with RTL and firmware engineers to resolve design defects and correct any test issues
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
  • Fulltime
Read More
Arrow Right

Senior ASIC verification Engineer

We are looking for a new ASIC Verification Engineer to become part of the future...
Location
Location
Costa Rica , Heredia
Salary
Salary:
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent
  • 6-10 years of experience in VLSI design, verification, or implementation
  • Expert level proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture
  • Expert level analytical and problem solving skills
  • Expert level knowledge of designing VLSI components, integrated circuitry, architectures and algorithms into VLSI solutions
  • Expert level knowledge of a programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools
  • Experience in executive written and verbal communication skills
  • mastery in English and local language
  • Subject matter expertise or discipline leadership as evidenced through patents/publications in the field of VSLI or Electronic/hardware component designs and tools
Job Responsibility
Job Responsibility
  • Provide technical expertise and leads project teams of Electronic and VLSI engineers and internal and outsourced development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing
  • Reviews and evaluates designs and project activities for compliance with VLSI technology and development guidelines and standards
  • provides tangible feedback to improve product quality
  • Provides VLSI-specific and technical expertise along with the overall architecture design and platform leadership to cross-organization projects, programs, and activities
  • Provides leadership of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products
  • Provides guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence
  • Participates in and provides input on process for selection of future technical leaders
  • Drives VLSI innovation and integration of new technologies into projects and activities in the design organization
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
  • Fulltime
Read More
Arrow Right

Senior Verification Design Engineer

The focus of this role is to plan, build, and execute the verification of new an...
Location
Location
Canada , BRITISH COLUMBIA
Salary
Salary:
124000.00 - 186000.00 CAD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proficient in IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches and working in Linux and Windows environments
  • Experienced with Verilog, System Verilog, C, and C++
  • Graphics pipeline knowledge
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Job Responsibility
Job Responsibility
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed and random verification tests
  • Debug test failures to determine the root cause
  • work with RTL and firmware engineers to resolve design defects and correct any test issues
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Read More
Arrow Right

Senior FPGA ASIC Design Engineer

Join a team at the forefront of computing innovation. This is an exceptional opp...
Location
Location
United Kingdom , Penicuik
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong experience with modern, complex digital processing architectures
  • Deep understanding of FPGA and ASIC design flows, tools, and system-level design
  • Solid software development and integration skills
  • A proven track record of technical leadership, mentoring engineers, and driving projects from concept to delivery
Job Responsibility
Job Responsibility
  • Lead technical discussions and collaborate with system architects, hardware, and software engineers to define and deliver new features
  • Act as a technical mentor to junior engineers through design reviews, best-practice guidance, and day-to-day support
  • Design and implement high-quality, high-performance RTL for new features, modules, and systems
  • Develop software and scripts to configure, control, and test hardware modules and systems
  • Create clear, detailed documentation describing designs and interactions with hardware and software components
  • Debug complex system-level issues, identify root causes, and partner with verification teams to deliver robust solutions
  • Estimate development schedules and test-environment needs, and support junior engineers with project planning
  • Champion continuous improvement in design, validation, and development workflows
  • Take on increasing leadership responsibilities, with a clear path toward senior technical or team management roles
  • Fulltime
Read More
Arrow Right

Asic / Physical Design Engineer (Int, Senior and Principal)

Location
Location
Canada , Ottawa
Salary
Salary:
Not provided
myticas.com Logo
Myticas Consulting
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8+ years in ASIC Physical Design / Backend Implementation (PnR)
  • End-to-end experience from netlist to GDSII (full physical design flow)
  • Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
  • Proven timing closure expertise (setup/hold, ECO implementation)
  • Deep experience with Synopsys and/or Cadence tool suites
  • Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
  • Strong Static Timing Analysis (STA) and timing report analysis
  • Experience with clock tree synthesis (CTS) and clock optimization
  • Solid understanding of DRC/LVS and physical verification flows
  • IR drop / power integrity analysis and optimization experience
  • Fulltime
Read More
Arrow Right

Senior Verification Engineer

System Validation engineers in this group are responsible for driving validation...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
arm.com Logo
ARM
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 4-6 Years of Experience
  • Bachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering
  • Experience of Emulation and system level validation for IPs and sub-systems and ASIC products
  • Emulation build skills and knowledge for a subsystem in at least one emulation system
  • Execution of the design in emulation platform and knowledge of hardware and software interplay
  • Knowledge of Validation test content using C, C++
  • Expertise on hardware behavioral language (Verilog, System Verilog)
  • Exposure to producing validation specifications and documentation describing sophisticated designs
  • Ability to work under time-scale pressure and meet ambitious targets without compromising on quality
  • Understanding of the fundamentals of computer architecture, system IP, memory subsystem, accelerator
Job Responsibility
Job Responsibility
  • Work with project team to understand, review the system requirements and deliver emulator testbench specifications
  • Own the development of validation platform in emulation, debug methodology, developing and implementing the test content, finding bugs, and running various validation checks for IPs (CPUs and SystemIPs), Interfaces (like CHI, PCIe etc.) in emulation environment
  • Guide other members of the team as needed to enable the successful completion of project activities
What we offer
What we offer
  • Health and Wellness
  • Work and Life Success
  • Financial Rewards
  • Development and Support
Read More
Arrow Right