CrawlJobs Logo

Senior Analog Design Engineer

United States, Agoura Hills Employment contract 123100.00 - 193900.00 USD / Year · Job Posted May 10, 2026
Apply Position
Job Link Share

Job Description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

Job Responsibility

  • Develop detailed circuit specifications for mixed signal circuits
  • Conceive circuit architectures and transistor level circuit topologies that satisfy required performance
  • Physical implementation (layout) of high speed circuits, either directly or assisting
  • Optimization of circuits via simulation (with Cadence EDA tools) over all process and operating conditions
  • Integration of circuit elements into large analog/mixed signals ASICs
  • Participation in the characterization of ASIC circuits

Requirements

  • MSEE with 5 years of experience or PhD in electrical engineering with 3 years experience in the design and characterization of multiple, high frequency and high scale of integration mixed signal integrated circuits
  • Thorough knowledge of high frequency, broad-band Analog Mixed-Signal IC design – both electrical and physical design
  • Desire experience in design of VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high frequency I/Os, high frequency CML designs, high voltage, power circuits
  • Solid understanding of CMOS semiconductor device physics and device modeling
  • Solid understanding of electromagnetic theory
  • Solid understanding of transmission line theory
  • Solid understanding of thermal effects of various circuit topologies and different package types
  • Involvement in all phases of multiple IC developments from specification to product introduction
  • Solid understanding and experience with IC characterization at high frequencies using high speed sampling oscilloscopes, spectrum analyzers, VNAs, signal sources
  • Solid understanding of working with PDKs
  • Ability to work well with a team
  • Good communicator

Nice to have

  • Experience with Cadence Skill or Ocean scripting for automating test benches is a plus
  • Proficiency in Verilog or Verilog-A modeling is highly desired
  • Direct experience in FINFET desired
  • Generic experience in deep sub-micron CMOS (nodes < 65 nm) highly desired
  • Experience in BCD technology is a plus
  • Experience with high voltage and/or mixed voltage domain circuit design is desired
  • Experience with ATE test development is a plus

What we offer

  • medical
  • dental
  • vision
  • Flexible Spending Accounts
  • retirement savings plans
  • life and disability insurance
  • paid vacation & holidays
  • tuition assistance programs

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Similar Jobs for

Senior Analog Design Engineer

8 matching positions

Senior Analog Design Engineer

For our customer, a leading global provider of microcontrollers and semiconducto...
Location
Location
Turkey , Istanbul
Salary
Salary:
Not provided
sHR Consultancy
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Typically 5 – 10 years of experience
  • Strong competence with various tools and procedures, reaching specialist level
  • Ability to work with minimal instruction – either independently or collaboratively
  • Ability to make good judgment in selecting methods/techniques for obtaining solutions
  • Able to confidently share own expertise and work to others
  • Able to make significant contribution to projects, programs and business initiatives with creativity and ingenuity
  • Ability to support and mentor less experienced team members
  • Cross cultural awareness and sensitivity
  • Results-oriented and able to deliver on-time under tight schedule
  • Ability to work both independently and part of a team
Job Responsibility
Job Responsibility
  • Design, verification, and simulation of CMOS Analog blocks for power management circuits including voltage references, bias circuits, comparators and amplifiers meeting performance, area and power specifications
  • Collaborate with block leads to achieve system and design strategy for power management products
  • Guide layout team to ensure quality of layout of own design
  • Drive silicon debugging and design characterization
  • Drive lab evaluation in collaboration with Application Engineers for own design
  • Produce high-quality documentation for own IP blocks
  • Working closely with DFT engineers to ensure that own blocks follow existing strategy and implementation for DFT
  • Work closely with test and product engineers to support test development and ramp to production
  • Coach and mentor less experienced team members
  • Contribute to schematic and layout block-level reviews for blocks initially designed by others
What we offer
What we offer
  • A competitive salary and benefits package
  • USD based compensation model
  • Educational and development opportunities
  • Hybrid working option
  • Fulltime
Read More
Arrow Right

Senior Analog Design Engineer

The Interface & Custom Circuit Engineering team in AI-Silicon Engineering is see...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BSEE or equivalent, MSEE/PhD preferred
  • 7+ years of experience in analog circuit design, through full cycle post BSEE or equivalent
  • Experience with high-speed analog front-end serdes or D2D design (preferably PCIe, UCIe, D-PHY, USB), data-converters, PLLs, Regulators and all associated blocks in analog designs from architecture till silicon validation support
  • Experience in Design partitioning, power/jitter budgeting and timing analysis
  • Knowledge of lower power design techniques, calibration, parasitic extraction, EM/IR/ESD/Aging & Signal Integrity Design
  • Experience with the use of CAD-tools (Cadence, Mentor, Synopsys) for circuit schematic entry, simulations, post layout extractions, Mixed-mode simulations
  • Delivered Analog IP’s successfully in mass production in FinFET processes
  • Experience in mentoring individual engineers
  • Working with multiple stakeholders (arch/design/layout/silicon validation/project managers) to execute full design cycle till silicon
  • Excellent communication skills and self-motivated that can collaborate with larger teams within Microsoft
Job Responsibility
Job Responsibility
  • Lead Analog designs and delivery of cutting edge, high-performance, high-speed, low-power Analog IP designs for interconnectivity solutions and fundamental Analog circuit blocks for various Microsoft products in various process nodes including deep FinFet, following industry best practices
  • Technically deliver complex blocks that will produce schematics, verify in simulation, complete timing/jitter/power budgets and work with mask layout teams to deliver a final IP GDS
  • Coordinate tasks with junior members of the team, develop plans for Analog IP execution, follow processes/methodologies to deliver IP blocks
  • Coordinate bench validation of IP in Silicon, and IP characterization on bench and tester
  • Use established flows/methodologies/processes for execution
  • Work along with other members of the team to deliver IP’s, including project planning, schedule tracking, report generation
  • Interface with RTL, Verification and P&R team
  • Fulltime
Read More
Arrow Right

Senior Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...
Location
Location
India , Hyderabad
Salary
Salary:
Not provided
synopsys.com Logo
Synopsis Engineering
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • MTech/MS with 2+ years or BTech/BS with 4+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
  • Proven expertise with FinFET technologies and CMOS tape-outs
  • Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
  • Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
  • Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
  • Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
  • Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
  • Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
  • Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
  • Excellent communication and documentation skills
Job Responsibility
Job Responsibility
  • Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
  • Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
  • Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
  • Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
  • Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
  • Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
  • Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates
What we offer
What we offer
  • Comprehensive medical and healthcare plans that work for you and your family
  • In addition to company holidays, we have ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Save for your future with our retirement plans that vary by region and country
  • Competitive salaries
  • Fulltime
Read More
Arrow Right

Senior Analog Layout Design Engineer

AMD is looking for a candidate to design the layout for digital and analog circu...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Must have detailed knowledge of CMOS circuit theory
  • Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
  • Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
  • Must have at least 5 years of relevant or comparable experience doing analog layout design
  • Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
  • Good understanding of signal and clock shielding and isolation techniques
  • Ability to work well as part of a team
  • Bachelor's degree in Engineering (or related field) OR Associates Degree in Engineering.
Job Responsibility
Job Responsibility
  • Layout of basic digital and analog building blocks using analog transistor level components
  • Layout of analog macros, power pads, and input/output pads using above blocks
  • Working closely with Analog designers in floorplanning
  • power grid and signal flow planning
  • Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
  • Creation of blackbox models for other groups in the design flow
  • Fulltime
Read More
Arrow Right

Senior Analog Mixed-Signal Design Engineer

We are looking for an experienced and highly driven Senior Analog Mixed-Signal D...
Location
Location
France , Paris; Caen; Grenoble
Salary
Salary:
Not provided
scalinx.com Logo
SCALINX
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proven track record of architecting, designing, and bringing to production multiple complex analog/mixed-signal ICs in advanced CMOS technologies
  • Deep expertise in high-speed, low-noise, and high-linearity analog circuit design
  • Strong technical leadership with a clear ownership mindset and accountability for deliverables
  • Excellent analytical, problem-solving, and debugging skills
  • Ability to mentor junior engineers and elevate overall team technical capability
  • Master's or PhD degree in Electrical Engineering or a related field, with a strong focus on analog/mixed-signal IC design
  • 10+ years of hands-on experience in analog/mixed-signal IC design in deep submicron CMOS technologies
  • Strong foundation in analog fundamentals including device physics, noise analysis, linearity, stability, mismatch, yield, and reliability
  • Extensive experience with transistor-level circuit design and simulation tools within the Cadence design suite (e.g., Virtuoso, Spectre), including corner and statistical verification methodologies
  • Proven experience designing high-performance blocks such as data converters, clocking circuits (PLLs/DLLs), high-speed interfaces, or precision analog front-ends
Job Responsibility
Job Responsibility
  • Lead the architecture definition and transistor-level design of high-performance analog and mixed-signal blocks including ADCs, DACs, PLLs, LDOs, bandgaps, amplifiers, comparators, clocking circuits, and complete data converter subsystems
  • Partner with system engineers and architects to translate system-level requirements into detailed circuit specifications and robust design implementations
  • Perform comprehensive transistor-level simulations and verification
  • Drive top-level integration of analog and mixed-signal subsystems
  • Collaborate closely with layout engineers to ensure optimal floorplanning, symmetry, matching, shielding, and parasitic-aware design techniques
  • Conduct post-layout simulations
  • Support silicon bring-up, lab validation, characterization, and root-cause debugging
  • Analyze silicon measurement results, ensure correlation with simulations
  • Contribute to and lead technical design reviews, risk assessments, and comprehensive documentation
  • Collaborate cross-functionally with digital design, verification, product engineering, and test teams
  • Fulltime
Read More
Arrow Right

Senior Staff Senior Silicon Design Automation Engineer

As a design engineer in our CAD and methodology team, you will be responsible fo...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • TCL, Python, PERL, or other scripting languages
  • PDK, technology enablement
  • Simulation environments for Spice, PVT
  • Virtuoso based custom Layout tools and flows
  • Calibre extraction flows, Totem & Redhawk for EM/IR
  • SiliconSmart, PrimeTimePhysical aspect of VLSI designs
  • Strong written and verbal communication skills
  • Bachelors or Masters degree in computer engineering/Electrical Engineering
Job Responsibility
Job Responsibility
  • Execute in CAD infrastructure team supporting multiple IC design projects
  • Establish and maintain standardized design flows and methodologies
  • Implement and support customized CAD flows for Fabric design groups
  • Enable the team in meeting the design and development targets by working closely with external tool vendors
  • Develop tools flows methodologies on digital back-end domains, sign-off flows for timing, power, EM/IR, DRC/LVS/DFM, etc.
  • Improve engineering efficiency while improving design quality in IP release process
  • Be single point contact for bugs and issues for custom and analog physical design team
  • Build flow in TCL, Python to ensure quality and faster executions
  • Understand different methodologies used across industry to adopt best practices
  • Leverage and deploy AMD AI systems to design teams
  • Fulltime
Read More
Arrow Right

Senior Engineer - Design for Test (DFT)

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Hillsboro
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • equivalent experience
  • 4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test
  • ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Microsoft Cloud Background Check
Job Responsibility
Job Responsibility
  • Own block level DFT u-arch specification documentation & provide Test solutions in design for test chips and products
  • Ensure DFX goals (testability, debug, manufacturability, System Test, System Debug, Repair) are met by these IPs, ensure analog to digital boundaries are reliably tested. Review coverage metrics for Digital logic
  • Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI
  • Provide test plans and engage closely with verification engineers to perform waveform reviews
  • Ensure RTL quality pre-DFT to ensure the RTL is good for DFT insertion and coverage
  • Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis
  • Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (Architects, front-end & back-end design/verification, Physical design, and post-silicon manufacturing) with respect and with One Microsoft mentality to establish synergies
  • Fulltime
Read More
Arrow Right

Asic / Physical Design Engineer (Int, Senior and Principal)

Location
Location
Canada , Ottawa
Salary
Salary:
Not provided
myticas.com Logo
Myticas Consulting
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8+ years in ASIC Physical Design / Backend Implementation (PnR)
  • End-to-end experience from netlist to GDSII (full physical design flow)
  • Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
  • Proven timing closure expertise (setup/hold, ECO implementation)
  • Deep experience with Synopsys and/or Cadence tool suites
  • Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
  • Strong Static Timing Analysis (STA) and timing report analysis
  • Experience with clock tree synthesis (CTS) and clock optimization
  • Solid understanding of DRC/LVS and physical verification flows
  • IR drop / power integrity analysis and optimization experience
  • Fulltime
Read More
Arrow Right